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2.4.4. Step 4: Create a Design Using Board and Preset Files
Once you create board and preset files, you can use these files to create a design that is appropriately configured for the target board. The following steps describe adding a new instance of the PIO (Parallel I/O) Intel FPGA that derives parameters from the pio_led preset and targets the same Intel Agilex F-Series Development Kit board.
- View the Clock Bridge Intel® FPGA IP, Reset Bridge Intel® FPGA IP, and PIO Intel® FPGA IP components in Platform Designer's System View.
- Right-click the PIO Intel® FPGA IP (pio_0) in the System View, and then click Remove.
- In the IP Catalog, click the Board tab.
- Under the Intel Agilex F-Series FPGA Development Kit DK-DEV-AGF014EA board, click NIOSV to expand the niosv_fseries_fpga_dev_kit_ocm_boot IP preset name. Click the IP preset name to show Nios V/m Processor Intel FPGA IP.
Figure 19. IP and Presets in Board Tab
- Double-click Nios V/m Processor Intel FPGA IP. The IP Parameter Editor opens.
- In the parameter editor Preset tab, double-click the preset name to apply to the selected IP (or click Apply in the Preset tab). The parameter editor displays the Preset tab with the active niosv_fseries_fpga_dev_kit_ocm_boot preset in bold.
Figure 20. Active Preset in Bold
- Click Finish to add the preset IP to the system.
- Repeat steps 4 through 6 to add the following IP with presets to the system. For the PIO Intel® FPGA IP, the external connection interface exports automatically per the pio_led preset.
Table 2. IP Components with Presets to Add to System Component Category IP Name IP Preset Name PIO PIO (Parallel I/O) Intel® FPGA IP pio_led OCM On-Chip Memory (RAM or ROM) Intel® FPGA IP ocm_fseries_fpga_dev_kit JTAG-UART JTAG UART Intel® FPGA IP juart_fseries_fpga_dev_kit - Make connections between the following component ports in the System View tab by clicking inside an open connection circle. When you make a connection, Platform Designer changes the connection line to black, and fills the connection circle. Clicking a filled-in circle removes the connection:
Table 3. System Connections Source Component/Signal Target Component/Signal clock_in.out_clk intel_niosv_m_0.clk
pio_0.clk
onchip_memory2_0.clk1
jtag_uart_0.clk
reset_in.out_reset intel_niosv_m_0.reset
pio_0.reset
onchip_memory2_0.reset1
jtag_uart_0.reset
jtag_uart_0.irq intel_niosv_m_0.platform_irq_rx
intel_niosv_m_0.instruction_manager intel_niosv_m_0.dm_agent
onchip_memory2_0.s1
intel_niosv_m_0.data_manager intel_niosv_m_0.timer_sw_agent
intel_niosv_m_0.dm_agent
pio_0.s1
onchip_memory2_0.s1
jtag_uart_0.avalon_jtag_slave
Figure 21. Completed System Connections
- To clear the remaining system warnings, assign the missing base addresses by clicking System > Assign Base Addresses.
- Click File > Save to save the system.
- Click the Generate > Generate HDL and generate the HDL for the system using default settings in the Generation dialog box.
- When HDL generation completes, close Platform Designer.