AN 988: Using the Board-Aware Flow: in the Intel® Quartus® Prime Pro Edition Software

Download PDF
ID 757339
Date 1/09/2023
Public
Document Table of Contents
Document Table of Contents x
1. Answers to Top FAQs 2. Using the Board-Aware Flow in the Intel® Quartus® Prime Pro Edition Software
2. Using the Board-Aware Flow in the Intel® Quartus® Prime Pro Edition Software x
2.1. Document Prerequisites 2.2. Downloading and Extracting Supporting Files 2.3. Accessing Intel FPGA Design Examples 2.4. Using the Board-Aware Flow in Platform Designer 2.5. Document Revision History of AN 988: Using the Board-Aware Flow in the Intel® Quartus® Prime Pro Edition Software
2.3. Accessing Intel FPGA Design Examples x
2.3.1. Accessing Pre-Installed Design Examples 2.3.2. Accessing Downloaded Design Examples 2.3.3. Accessing Online Design Examples
2.4. Using the Board-Aware Flow in Platform Designer x
2.4.1. Step 1: Specify a Target Board for the Project 2.4.2. Step 2: Create a New Board File 2.4.3. Step 3: Create IP Presets for the Board 2.4.4. Step 4: Create a Design Using Board and Preset Files 2.4.5. Step 5: Compile and Verify the Design 2.4.6. Step 6: Configure the Board with Software
1. Answers to Top FAQs
2. Using the Board-Aware Flow in the Intel® Quartus® Prime Pro Edition Software

2.3.2. Accessing Downloaded Design Examples

You can create a new project based on a design example that you have previously downloaded. To test this method, you can download a design example .par file from the Intel FPGA Design Store, or from another online repository that stores design examples in .par format, into your working directory. Platform Designer also classifies designs that you create yourself and store in a local drive as downloaded examples.

To create a new project based on a downloaded design example, follow these steps:

  1. Start the Intel® Quartus® Prime Pro Edition software.
  2. Click File > Open Example Project. The Design Example page of the New Project Wizard opens.
  3. Under What is the working directory for this project?, specify the directory location to store your project files.
  4. Click the Design Store button. The Design Store web page displays an unfiltered list of available design examples.
    Figure 4. Design Store Listing Available Design Examples


  5. From the left navigation menu, click on Agilex FPGAs and SOC FPGAs to filter the list of design examples.
  6. Click the I/O PLL Reconfiguration design example.
  7. Download the .par file for the I/O PLL Reconfiguration design example to your working directory. Accept the license agreement when prompted.
  8. On the Design Example page, click the More Settings button.
  9. Click the Design Examples Search Locations tab.
  10. In the Design examples search directories box, specify the working directory to store your downloaded design example .par file from step 3.
  11. Under Find Options, specify the following settings:
    1. In Load from, select Downloaded design examples.
    2. In Family, select Agilex.
    3. In Intel Quartus Prime version, select 19.4.
    4. In Development kit, select Agilex F-series Transceiver-SoC Development Kit.
  12. In the design example list, select the I/O PLL Reconfiguration design. The ? symbol indicates that the design is not yet validated for the current Intel® Quartus® Prime software version.
    Figure 5. Downloaded Agilex I/O PLL Reconfiguration Design


  13. Click Next, and then click Finish. The I/O PLL Reconfiguration design extracts to the working directory and opens in the Intel® Quartus® Prime software.
Level Two Title