Visible to Intel only — GUID: tyc1662431351621
Ixiasoft
1. Quick Start Guide
2. F-Tile 25G Ethernet Single-Channel Design Example
3. F-Tile 25G Ethernet Single Channel Design Example with Dynamic Reconfiguration
4. F-Tile 25G Ethernet Intel FPGA IP Design Example User Guide Archives
5. Document Revision History for F-Tile 25G Ethernet Intel® FPGA IP Design Example User Guide
1.1. Directory Structure
1.2. Generating the Design Example
1.3. Generating Tile Files
1.4. Simulating the F-Tile 25G Ethernet Intel FPGA IP Design Example Testbench
1.5. Compiling and Configuring the Design Example in Hardware
1.6. Testing the F-Tile 25G Ethernet Intel FPGA IP Hardware Design Example
Visible to Intel only — GUID: tyc1662431351621
Ixiasoft
1.6. Testing the F-Tile 25G Ethernet Intel FPGA IP Hardware Design Example
After you compile the F-Tile 25G Ethernet Intel FPGA IP core design example and configure it on your Intel Agilex® 7 device, you can use the System Console to program the IP core.
To turn on the System Console and test the hardware design example, follow these steps:
- In the Intel® Quartus® Prime Pro Edition software, select Tools > System Debugging Tools > System Console to launch the system console.
- In the Tcl Console pane, type cd hwtest to change directory to /hardware_test_design/hwtest.
- Type source main.tcl to open a connection to the JTAG master.
Follow the test procedure in the Hardware Testing section of the design example and observe the test results in the System Console.