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1. Quick Start Guide
2. F-Tile 25G Ethernet Single-Channel Design Example
3. F-Tile 25G Ethernet Single Channel Design Example with Dynamic Reconfiguration
4. F-Tile 25G Ethernet Intel FPGA IP Design Example User Guide Archives
5. Document Revision History for F-Tile 25G Ethernet Intel® FPGA IP Design Example User Guide
1.1. Directory Structure
1.2. Generating the Design Example
1.3. Generating Tile Files
1.4. Simulating the F-Tile 25G Ethernet Intel FPGA IP Design Example Testbench
1.5. Compiling and Configuring the Design Example in Hardware
1.6. Testing the F-Tile 25G Ethernet Intel FPGA IP Hardware Design Example
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1.5. Compiling and Configuring the Design Example in Hardware
The 25G Ethernet Intel FPGA IP core parameter editor allows you to compile and configure the design example on a target development kit.
To compile and configure a design example on hardware, follow these steps:
- Launch the Intel® Quartus® Prime Pro Edition software and select Processing > Start Compilation to compile the design.
- After you generate an SRAM object file .sof, follow these steps to program the hardware design example on the Intel Agilex® 7 device:
- On the Tools menu, click Programmer.
- In the Programmer, click Hardware Setup.
- Select a programming device.
- Select and add the Intel Agilex® 7 board to your Intel® Quartus® Prime Pro Edition session.
- Ensure that Mode is set to JTAG.
- Select the Intel Agilex® 7 device and click Add Device. The Programmer displays a block diagram of the connections between the devices on your board.
- In the row with your .sof, check the box for the .sof.
- Check the box in the Program/Configure column.
- Click Start.