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1.5.1. Step 1: Getting Started
1.5.2. Step 2: Create Design Partitions
1.5.3. Step 3: Allocate Placement and Routing Regions
1.5.4. Step 4: Define Personas
1.5.5. Step 5: Create Revisions
1.5.6. Step 6: Compile the Base Revision
1.5.7. Step 7: Set Up PR Implementation Revisions
1.5.8. Step 8: Change the SUPR Logic
1.5.9. Step 9: Program the Board
1.5.10. Modifying the SUPR Partition
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1.5.5. Step 5: Create Revisions
The PR design flow uses the project revisions feature in the Intel® Quartus® Prime software. Your initial design is the base revision, where you define the static region boundaries and reconfigurable regions on the FPGA.
From the base revision, you create additional revisions. These revisions contain the different implementations for the PR regions. However, all PR implementation revisions use the same top-level placement and routing results from the base revision.
To compile a PR design, you create a PR implementation revision for each persona. In addition, you must assign either the Partial Reconfiguration - Base or Partial Reconfiguration - Persona Implementation revision type for each of the revisions. The following table lists the revision name and the revision type for each of the revisions. The impl_blinking_led_supr_new.qsf revision is the SUPR persona implementation.
| Revision Name | Revision Type |
|---|---|
| blinking_led | Partial Reconfiguration - Base |
| blinking_led_default | Partial Reconfiguration - Persona Implementation |
| blinking_led_slow | Partial Reconfiguration - Persona Implementation |
| blinking_led_empty | Partial Reconfiguration - Persona Implementation |
| impl_blinking_led_supr_new | Partial Reconfiguration - Persona Implementation |