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1.5.1. Step 1: Getting Started
1.5.2. Step 2: Create Design Partitions
1.5.3. Step 3: Allocate Placement and Routing Regions
1.5.4. Step 4: Define Personas
1.5.5. Step 5: Create Revisions
1.5.6. Step 6: Compile the Base Revision
1.5.7. Step 7: Set Up PR Implementation Revisions
1.5.8. Step 8: Change the SUPR Logic
1.5.9. Step 9: Program the Board
1.5.10. Modifying the SUPR Partition
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1.6. Document Revision History of AN 987: Static Update Partial Reconfiguration Tutorial for Intel Agilex® 7 FPGA Development Board
Document Version | Intel® Quartus® Prime Version | Changes |
---|---|---|
2024.01.16 | 23.3 |
|
2022.10.24 | 22.3 | Initial release of the document. |