Triple-Speed Ethernet Intel Agilex FPGA IP Design Example User Guide

Download PDF
ID 741330
Date 12/09/2022
Public

A newer version of this document is available. Customers should click here to go to the newest version.

Document Table of Contents
Document Table of Contents x
1. Quick Start Guide 2. 10/100/1000 Multiport Ethernet MAC Design Example with 1000BASE-X/SGMII PCS and Embedded PMA 3. Document Revision History for the Triple-Speed Ethernet Intel® FPGA IP Intel® Agilex™ Design Example User Guide
1. Quick Start Guide x
1.1. Directory Structure 1.2. Generating the Design Example 1.3. Simulating the Triple-Speed Ethernet Intel® FPGA IP Design Example Testbench 1.4. Compiling and Configuring the Design Example in Hardware
1.2. Generating the Design Example x
1.2.1. Design Example Parameters
2. 10/100/1000 Multiport Ethernet MAC Design Example with 1000BASE-X/SGMII PCS and Embedded PMA x
2.1. Features 2.2. Hardware and Software Requirements 2.3. Functional Description 2.4. Simulation
2.3. Functional Description x
2.3.1. Design Components 2.3.2. Clock and Reset Signals
2.4. Simulation x
2.4.1. Testbench
1. Quick Start Guide
2. 10/100/1000 Multiport Ethernet MAC Design Example with 1000BASE-X/SGMII PCS and Embedded PMA
3. Document Revision History for the Triple-Speed Ethernet Intel® FPGA IP Intel® Agilex™ Design Example User Guide

1.4. Compiling and Configuring the Design Example in Hardware

To compile the hardware design example and configure it on your Intel® Agilex™ device, follow these steps:

  1. Ensure hardware design example generation is complete.
  2. In the Intel® Quartus® Prime Pro Edition software, open the Intel® Quartus® Prime project <design_example_dir>/hardware_test_design/altera_eth_tse_hw.qpf .
  3. On the Processing menu, click Start Compilation.
  4. After a successful compilation, a.sof file is available in <design_example_dir>/hardwarde_test_design directory.
Level Two Title