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1. About the Nios® V Embedded Processor
2. Nios® V Processor Hardware System Design with Quartus® Prime Software and Platform Designer
3. Nios® V Processor Software System Design
4. Nios® V Processor Configuration and Booting Solutions
5. Nios® V Processor - Using the MicroC/TCP-IP Stack
6. Nios® V Processor Debugging, Verifying, and Simulating
7. Nios® V Processor — Remote System Update
8. Nios® V Processor — Using Custom Instruction
9. Nios® V Embedded Processor Design Handbook Archives
10. Document Revision History for the Nios® V Embedded Processor Design Handbook
2.1. Creating Nios® V Processor System Design with Platform Designer
2.2. Integrating Platform Designer System into the Quartus® Prime Project
2.3. Designing a Nios® V Processor Memory System
2.4. Clocks and Resets Best Practices
2.5. Assigning a Default Agent
2.6. Assigning a UART Agent for Printing
2.7. JTAG Signals
4.1. Introduction
4.2. Linking Applications
4.3. Nios® V Processor Booting Methods
4.4. Introduction to Nios® V Processor Booting Methods
4.5. Nios® V Processor Booting from Configuration QSPI Flash
4.6. Nios® V Processor Booting from On-Chip Memory (OCRAM)
4.7. Nios® V Processor Booting from Tightly Coupled Memory (TCM)
4.8. Summary of Nios® V Processor Vector Configuration and BSP Settings
6.2.3.2.1. Enabling Signal Tap Logic Analyzer
6.2.3.2.2. Adding Signals for Monitoring and Debugging
6.2.3.2.3. Specifying Trigger Conditions
6.2.3.2.4. Assigning the Acquisition Clock, Sample Depth, and Memory Type, and Buffer Acquisition Mode
6.2.3.2.5. Compiling the Design and Programming the Target Device
6.6.1. Prerequisites
6.6.2. Setting Up and Generating Your Simulation Environment in Platform Designer
6.6.3. Creating Nios V Processor Software
6.6.4. Generating Memory Initialization File
6.6.5. Generating System Simulation Files
6.6.6. Running Simulation in the QuestaSim Simulator Using Command Line
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7.3.5.3. Generating a Factory Update Flash Image
- On the File menu, click Programming File Generator.
- Select Active Serial x4 from the Configuration mode drop-down list. The current Quartus® Prime software only supports remote system update feature in Active Serial x4.
- On the Output Files tab, assign the output directory and file name.
- Select the output file type as Raw Programming File (.rpd).
- By default, the .rpd file type is little-endian. Set the Bit swap to On.
Note: If you are using a third-party programmer that does not support the little-endian format, set the Bit swap to On to generate the .rpd file in big endian format.Figure 132. Programming File Generator (Output Files)
- On the Input Files tab, click Add Bitstream. Change the Files of type to SRAM Object File (*.sof). Then, select factory update image .sof file (application-2.sof) and click Open.
Figure 133. Programming File Generator (Input Files)
- Select the application-2.sof and then click Properties. Turn on Generate RSU factory update image.
Figure 134. Generate RSU Factory Update Image
- Click Generate to generate the RSU programming files. You can now update the decision firmware, decision firmware data, and the factory image into the initial RSU image.
Command to generate factory update image
quartus_pfg -c application-2.sof factory_update.rpd -o mode=ASX4 -o bitswap=ON -o rsu_upgrade=ON