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1. About the Nios® V Embedded Processor
2. Nios® V Processor Hardware System Design with Quartus® Prime Software and Platform Designer
3. Nios® V Processor Software System Design
4. Nios® V Processor Configuration and Booting Solutions
5. Nios® V Processor - Using the MicroC/TCP-IP Stack
6. Nios® V Processor Debugging, Verifying, and Simulating
7. Nios® V Processor — Remote System Update
8. Nios® V Processor — Using Custom Instruction
9. Nios® V Embedded Processor Design Handbook Archives
10. Document Revision History for the Nios® V Embedded Processor Design Handbook
2.1. Creating Nios® V Processor System Design with Platform Designer
2.2. Integrating Platform Designer System into the Quartus® Prime Project
2.3. Designing a Nios® V Processor Memory System
2.4. Clocks and Resets Best Practices
2.5. Assigning a Default Agent
2.6. Assigning a UART Agent for Printing
2.7. JTAG Signals
4.1. Introduction
4.2. Linking Applications
4.3. Nios® V Processor Booting Methods
4.4. Introduction to Nios® V Processor Booting Methods
4.5. Nios® V Processor Booting from Configuration QSPI Flash
4.6. Nios® V Processor Booting from On-Chip Memory (OCRAM)
4.7. Nios® V Processor Booting from Tightly Coupled Memory (TCM)
4.8. Summary of Nios® V Processor Vector Configuration and BSP Settings
6.2.3.2.1. Enabling Signal Tap Logic Analyzer
6.2.3.2.2. Adding Signals for Monitoring and Debugging
6.2.3.2.3. Specifying Trigger Conditions
6.2.3.2.4. Assigning the Acquisition Clock, Sample Depth, and Memory Type, and Buffer Acquisition Mode
6.2.3.2.5. Compiling the Design and Programming the Target Device
6.6.1. Prerequisites
6.6.2. Setting Up and Generating Your Simulation Environment in Platform Designer
6.6.3. Creating Nios V Processor Software
6.6.4. Generating Memory Initialization File
6.6.5. Generating System Simulation Files
6.6.6. Running Simulation in the QuestaSim Simulator Using Command Line
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3.2. Intel FPGA Embedded Development Tools
The Nios® V processor supports the following tools for software development:
- Graphical User Interface (GUI) - Graphical development tools that are available in both Windows* and Linux* Operating Systems (OS).
- Nios V Board Support Package Editor (Nios V BSP Editor)
- Ashling* RiscFree* IDE for Intel FPGAs
- Command-Line Tools (CLI) - Development tools that are initiated from the Nios V Command Shell. Each tool provides its own documentation in the form of help accessible from the command line. Open the Nios V Command Shell and type the following command: <name of tool> --help to view the Help menu.
- Nios V Utilities Tools
- File Format Conversion Tools
- Other Utilities Tools
Task | GUI Tool | Command-line Tool |
---|---|---|
Creating a BSP | Nios V BSP Editor |
|
Generating a BSP using existing .bsp file | Nios V BSP Editor | niosv-bsp -g [OPTIONS] settings.bsp |
Updating a BSP | Nios V BSP Editor | niosv-bsp -u [OPTIONS] settings.bsp |
Examining a BSP | Nios V BSP Editor | niosv-bsp -q -E=<tcl script> [OPTIONS] settings.bsp |
Creating an application | - | niosv-app -a=<application directory> -b=<bsp directory> -s=<source files directory> [OPTIONS] |
Creating a user library | - | niosv-app -l=<library directory> -s=<source files directory> -p=<public includes directory> [OPTIONS] |
Modifying an application | RiscFree* IDE for Intel FPGAs | Any command-line source editor |
Modifying a user library | RiscFree* IDE for Intel FPGAs | Any command-line source editor |
Building an application | RiscFree* IDE for Intel FPGAs |
|
Building a user library | RiscFree* IDE for Intel FPGAs |
|
Downloading an application ELF | RiscFree* IDE for Intel FPGAs | niosv-download |
Converting the .elf file | - |
|