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Visible to Intel only — GUID: bxa1638416490009
Ixiasoft
2.1.2. Defining System Component Design
Use the Platform Designer to define the hardware characteristics of the Nios® V processor system and add in the desired components. The following diagram demonstrates a basic Nios® V processor system design with the following components:
- Nios® V processor core
- On-Chip Memory
- JTAG UART
- Interval Timer (optional)1
When a new On-Chip Memory is added to a Platform Designer system, perform Sync System Infos to reflect the added memory components in reset. Alternatively, you can enable Auto Sync in Platform Designer to automatically reflect the latest component changes
You must also define operation pins to export as conduit in your Platform Designer system. For example, a proper FPGA system operation pin list is defined as below but not limited to:
- Clock
- Reset
- I/O signals