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1. About the Nios® V Embedded Processor
2. Nios® V Processor Hardware System Design with Quartus® Prime Software and Platform Designer
3. Nios® V Processor Software System Design
4. Nios® V Processor Configuration and Booting Solutions
5. Nios® V Processor - Using the MicroC/TCP-IP Stack
6. Nios® V Processor Debugging, Verifying, and Simulating
7. Nios® V Processor — Remote System Update
8. Nios® V Processor — Using Custom Instruction
9. Nios® V Embedded Processor Design Handbook Archives
10. Document Revision History for the Nios® V Embedded Processor Design Handbook
2.1. Creating Nios® V Processor System Design with Platform Designer
2.2. Integrating Platform Designer System into the Quartus® Prime Project
2.3. Designing a Nios® V Processor Memory System
2.4. Clocks and Resets Best Practices
2.5. Assigning a Default Agent
2.6. Assigning a UART Agent for Printing
2.7. JTAG Signals
4.1. Introduction
4.2. Linking Applications
4.3. Nios® V Processor Booting Methods
4.4. Introduction to Nios® V Processor Booting Methods
4.5. Nios® V Processor Booting from Configuration QSPI Flash
4.6. Nios® V Processor Booting from On-Chip Memory (OCRAM)
4.7. Nios® V Processor Booting from Tightly Coupled Memory (TCM)
4.8. Summary of Nios® V Processor Vector Configuration and BSP Settings
6.2.3.2.1. Enabling Signal Tap Logic Analyzer
6.2.3.2.2. Adding Signals for Monitoring and Debugging
6.2.3.2.3. Specifying Trigger Conditions
6.2.3.2.4. Assigning the Acquisition Clock, Sample Depth, and Memory Type, and Buffer Acquisition Mode
6.2.3.2.5. Compiling the Design and Programming the Target Device
6.6.1. Prerequisites
6.6.2. Setting Up and Generating Your Simulation Environment in Platform Designer
6.6.3. Creating Nios V Processor Software
6.6.4. Generating Memory Initialization File
6.6.5. Generating System Simulation Files
6.6.6. Running Simulation in the QuestaSim Simulator Using Command Line
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7.3.3.4. Creating Multiple Application Projects
- Download the example source code using the link below.
- Navigate to the software/app folder and copy the example source codes.
- Change the default name of Mailbox Client Intel FPGA IP (MAILBOX_NAME) based on the system.h file, in the following locations:
- The example source codes
- Example Source Codes (application.c and factory.c)
int main(void) { … fd = mailbox_client_open(MAILBOX_NAME); … }
- Example Source Codes (application.c and factory.c)
- bsp/drivers/src/altera_s10_mailbox_client_flash_rsu.c
-
int plat_qspi_init(struct qspi_ll_intf **qspi_intf) { … #ifdef MAILBOX_NAME /* retrieve data from flash */ fd = mailbox_client_open(MAILBOX_NAME); #endif … }
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- bsp/drivers/src/altera_s10_mailbox_client_rsu.c
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int plat_mbox_init(struct mbox_ll_intf **mbox_intf) { … #ifdef MAILBOX_NAME fd = mailbox_client_open(MAILBOX_NAME); #endif … }
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- The example source codes
- Launch the Nios V Command Shell.
- Execute the command below to generate the user application CMakeLists.txt.
//For Application Image niosv-app --app-dir=software/app --bsp-dir=software/bsp \ --srcs=software/app/application.c,zlib/crc32.c \ --incs=zlib //For Factory Image niosv-app --app-dir=software/app --bsp-dir=software/bsp \ --srcs=software/app/factory.c,zlib/crc32.c \ --incs=zlib
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