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1. About the Nios® V Embedded Processor
2. Nios® V Processor Hardware System Design with Quartus® Prime Software and Platform Designer
3. Nios® V Processor Software System Design
4. Nios® V Processor Configuration and Booting Solutions
5. Nios® V Processor - Using the MicroC/TCP-IP Stack
6. Nios® V Processor Debugging, Verifying, and Simulating
7. Nios® V Processor — Remote System Update
8. Nios® V Processor — Using Custom Instruction
9. Nios® V Embedded Processor Design Handbook Archives
10. Document Revision History for the Nios® V Embedded Processor Design Handbook
2.1. Creating Nios® V Processor System Design with Platform Designer
2.2. Integrating Platform Designer System into the Quartus® Prime Project
2.3. Designing a Nios® V Processor Memory System
2.4. Clocks and Resets Best Practices
2.5. Assigning a Default Agent
2.6. Assigning a UART Agent for Printing
2.7. JTAG Signals
4.1. Introduction
4.2. Linking Applications
4.3. Nios® V Processor Booting Methods
4.4. Introduction to Nios® V Processor Booting Methods
4.5. Nios® V Processor Booting from Configuration QSPI Flash
4.6. Nios® V Processor Booting from On-Chip Memory (OCRAM)
4.7. Nios® V Processor Booting from Tightly Coupled Memory (TCM)
4.8. Summary of Nios® V Processor Vector Configuration and BSP Settings
6.2.3.2.1. Enabling Signal Tap Logic Analyzer
6.2.3.2.2. Adding Signals for Monitoring and Debugging
6.2.3.2.3. Specifying Trigger Conditions
6.2.3.2.4. Assigning the Acquisition Clock, Sample Depth, and Memory Type, and Buffer Acquisition Mode
6.2.3.2.5. Compiling the Design and Programming the Target Device
6.6.1. Prerequisites
6.6.2. Setting Up and Generating Your Simulation Environment in Platform Designer
6.6.3. Creating Nios V Processor Software
6.6.4. Generating Memory Initialization File
6.6.5. Generating System Simulation Files
6.6.6. Running Simulation in the QuestaSim Simulator Using Command Line
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5.7.1. Configuring Hardware Name
The global structure of type "alt_tse_system_info" (named "tse_mac_device") reflects the IP names according to the system.h file. If you change the default IP names or not using the default hardware project, you must update the following names in main.c source code. You can find the source code in the software/apps folder.
The latest IP names can be found in the system.h file after the hardware compilation in Quartus® Prime software. The header file is located in the BSP folder.
The following table lists the example design and the default IP names.
Example Design | IP Name |
---|---|
TSE | SYS_TSE |
TX MSGDMA | SYS_TSE_MSGDMA_TX |
RX MSGDMA | SYS_TSE_MSGDMA_RX |
Descriptor Memory | SYS_DESC_MEM |
Figure 101. Example Design Platform Designer System
Default Hardware Names in main.c
alt_tse_system_info tse_mac_device[MAXNETS] = { TSE_SYSTEM_EXT_MEM_NO_SHARED_FIFO( SYS_TSE, // tse_name 0, // offset SYS_TSE_MSGDMA_TX, // msgdma_tx_name SYS_TSE_MSGDMA_RX, // msgdma_rx_name TSE_PHY_AUTO_ADDRESS, // phy_addr NULL, // phy_cfg_fp SYS_DESC_MEM // desc_mem_name ) };