Visible to Intel only — GUID: yet1716984726408
Ixiasoft
Visible to Intel only — GUID: yet1716984726408
Ixiasoft
6.2.3.2.3.1. Basic Trigger Conditions
You can specify the trigger pattern for a single wire as Don’t Care, Low, High, Falling Edge, Rising Edge, or Either Edge.
Examples of single wires are:
- D_instr_valid
- E_instr_valid
- M0_instr_valid
For buses, you can select Insert Value to enter the pattern in any preferred number formats. Example of buses are:
- D_instr_pc[31..0]
- D_instr_word[31..0]
- E_instr_pc[6..0]
- E_instr_word[31..0]
- M0_instr_pc[31..0]
- Pick any pipeline stage as the trigger stage and leave other stages with disabled Trigger Enable.
- Specify the trigger pattern of its Instruction Valid as High.
- Specify a trigger value on the Program Counter by referring to the application objdump file. Refer to Correlating Trace Data to Software ELF on instruction trace and objdump file.
The following example selects the M-stage as the triggering stage.
Setting Up Triggering Stage based on objdump File
<Address>: <Opcode> <Assembly Mnemonic> 314 : ff010113 addi sp,sp,-16
- *_instr_pc[31..0] to 0x314
- *_instr_word[31..0] to 0xff010113