F-Tile PMA and FEC Direct PHY Multirate Intel® FPGA IP User Guide

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ID 720998
Date 4/01/2024
Public
Document Table of Contents
Document Table of Contents x
1. Introduction 2. Interface Overview 3. Parameters 4. Designing with the IP Core 5. Block Description 6. Configuration Registers Overview 7. F-Tile PMA and FEC Direct PHY Multirate Intel® FPGA IP User Guide Archives 8. Document Revision History for the F-Tile PMA and FEC Direct PHY Multirate Intel® FPGA IP User Guide
1. Introduction x
1.1. IP Core Overview 1.2. Release Information 1.3. Device Family Support 1.4. Device Speed Grade Support 1.5. Resource Utilization 1.6. Related Documentation
1.1. IP Core Overview x
1.1.1. Reconfiguration Group 1.1.2. Base Profile 1.1.3. Secondary Profiles 1.1.4. Startup Profile 1.1.5. Supported Reconfiguration Groups
2. Interface Overview x
2.1. Clock Signals 2.2. Reset Signals 2.3. TX and RX Parallel and Serial Signals 2.4. Custom Cadence Control and Status Signals 2.5. TX and RX PMA Status Signals 2.6. RS-FEC Signals 2.7. TX and RX PMA FIFO Signals 2.8. PMA Avalon Memory-Mapped Signals 2.9. Datapath Avalon Memory-Mapped Signals
3. Parameters x
3.1. Dynamic Reconfiguration QSF Settings 3.2. QSF settings for Different Reconfiguration Profiles 3.3. Generating IP-XACT File
3.2. QSF settings for Different Reconfiguration Profiles x
3.2.1. Bypass RX Adaptation QSF Settings
4. Designing with the IP Core x
4.1. Installing and Licensing Intel® FPGA IP Cores 4.2. Specifying the IP Core Parameters and Options 4.3. Generated File Structure 4.4. Configuring the F-Tile PMA/FEC Direct PHY Multirate Intel FPGA IP Core
4.1. Installing and Licensing Intel® FPGA IP Cores x
4.1.1. Intel® FPGA IP Evaluation Mode
4.2. Specifying the IP Core Parameters and Options x
4.2.1. Reference and System PLL Clock for your IP Design
4.4. Configuring the F-Tile PMA/FEC Direct PHY Multirate Intel FPGA IP Core x
4.4.1. Steps to Configure the F-Tile PMA/FEC Direct PHY Multirate Intel FPGA IP Core
6. Configuration Registers Overview x
6.1. Controlling the Reconfiguration Soft CSR Registers for Dynamic Reconfiguration 6.2. Configuration Registers
6.2. Configuration Registers x
6.2.1. F-Tile PMA/FEC Direct PHY Intel FPGA IP Core Soft CSR Registers 6.2.2. F-Tile PMA/FEC Direct PHY Multirate Intel® FPGA IP Core Soft CSR Registers
6.2.1. F-Tile PMA/FEC Direct PHY Intel FPGA IP Core Soft CSR Registers x
6.2.1.1. Controlling the Reconfiguration Soft CSR with Fractures
1. Introduction
2. Interface Overview
3. Parameters
4. Designing with the IP Core
5. Block Description
6. Configuration Registers Overview
7. F-Tile PMA and FEC Direct PHY Multirate Intel® FPGA IP User Guide Archives
8. Document Revision History for the F-Tile PMA and FEC Direct PHY Multirate Intel® FPGA IP User Guide

3.2. QSF settings for Different Reconfiguration Profiles

In addition to the general QSF setting, there are applications where one of the PMA lanes may need to reconfigure to lower data rates which would require bypassing the RX auto adaptation. The FGT PMA uses automatic RX adaptation, unless you add QSF assignments in the .qsf file.

You need to add QSF settings based on the profile information to bypass the RX adaptation for the PMA lanes. To add the QSF settings, you have to get the <top_level_instantiation_name> and the profile information from the <top>.tlg.rpt file by searching for BB_F_UX_TX and BB_F_UX_RX instantiations and profile names for the TX and RX respectively.

The <top>.tlg.rpt file has the path in the following format:
  • <top_level_instantiation_name> : F-Tile PMA/FEC Direct PHY Multirate Intel® FPGA IP top level instantiation name.
  • <x> : secondary profile number starts from 1 (up to the maximum profiles configured).
  • <n> : in perxcvr[n], n is the PMA lane count. Use 0 for a single PMA lane configuration. For profiles configuring multiple PMA lanes, this is 1..<n-1> up to the maximum PMA lane count set in that profile with same Profile Group ID.
An example of the <top>.tlg.rpt file with a search for BB_F_UX_TX instance is shown below: 
; -- BB_F_UX_TX ; dut|directphy_f_dr_0|U_sec_profile2|sec_profile_2|dphy_hip_inst|persystem[0].perxcvr[2].fgt.tx_ux.x_bb_f_ux_tx ;
In the example above, the BB_F_UX_TX instance from the <top>.tlg.rpt file contains the reconfiguration profile settings of:
  • <top_level_instantiation_name> : dut
  • <x> : secondary profile = 2
  • <n> : PMA lane count number = 3, in perxcvr[2]

Section Content
Bypass RX Adaptation QSF Settings

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