Visible to Intel only — GUID: etp1487061903229
Ixiasoft
1. About the F-Tile Low Latency Ethernet 10G MAC Intel® FPGA IP Design Example User Guide
2. Quick Start Guide
3. 10M/100M/1G/2.5G/5G/10G (USXGMII) Ethernet Design Example
4. Interface Signals Description
5. Configuration Registers Description
6. F-Tile Low Latency Ethernet 10G MAC Intel FPGA IP Design Example User Guide Archives
7. Document Revision History for the F-Tile Low Latency Ethernet 10G MAC Intel® FPGA IP Design Example User Guide
Visible to Intel only — GUID: etp1487061903229
Ixiasoft
4.8. TOD Interface Signals
Signal | Direction | Width | Description |
---|---|---|---|
master_pulse_per_second | Out | 1 | Pulse per second (PPS) from the master PPS module. The signal stay asserted for 10 ms. |
start_tod_sync[] | In | [NUM_CHANNELS] | Use this signal to trigger the TOD synchronization process. The time-of-day of the local TOD is synchronized to the time-of-day of the master TOD. The synchronization process continues as long as this signal remains asserted. |
pulse_per_second | Out | [NUM_CHANNELS] | PPS from channel n. The signal stay asserted for 10 ms. |