F-Tile Ethernet Multirate Intel® FPGA IP User Guide

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ID 714307
Date 5/01/2024
Public
Document Table of Contents
Document Table of Contents x
1. Introduction 2. Interface Overview 3. Parameters 4. Designing with the IP Core 5. Block Description 6. Configuration Registers 7. F-Tile Ethernet Multirate Intel FPGA IP User Guide Archives 8. Document Revision History for the F-Tile Ethernet Multirate Intel FPGA IP User Guide
1. Introduction x
1.1. Overview 1.2. Release Information 1.3. Device Family Support 1.4. Device Speed Grade Support 1.5. Resource Utilization 1.6. Related Documentation 1.7. F-Tile Ethernet Multirate IP Core Features and Constraints 1.8. F-Tile Ethernet Multirate IP Core Concepts
1.8. F-Tile Ethernet Multirate IP Core Concepts x
1.8.1. Reconfiguration Group 1.8.2. Base Profile 1.8.3. Secondary Profile 1.8.4. Secondary Profile Group 1.8.5. Startup Profile 1.8.6. Supported Reconfiguration Groups 1.8.7. PTP Timestamp Accuracy Support 1.8.8. Transceiver Lane Mapping
2. Interface Overview x
2.1. Port Numbering Scheme 2.2. Clock Signals 2.3. Reset Signals 2.4. Fractured MAC Segmented Interface for FGT Transceivers 2.5. Fractured MAC Segmented Interface for FHT Transceivers 2.6. Fractured MAC Avalon ST Client Interface for FGT Transceivers 2.7. Fractured MAC Avalon ST Client Interface for FHT Transceivers 2.8. Fractured MII PCS-Only Interface for FGT Transceivers 2.9. Fractured MII PCS-Only Interface for FHT Transceivers 2.10. Fractured PCS66 Interface for OTN/FlexE for FGT Transceivers 2.11. Fractured PCS66 Interface for OTN/FlexE for FHT Transceivers 2.12. MAC Flow Control Interface 2.13. Status Interface 2.14. Avalon® Memory-Mapped Reconfiguration Interfaces 2.15. Auto-Negotiation and Link Training Interface 2.16. Precision Time Protocol Interface
2.16. Precision Time Protocol Interface x
2.16.1. PTP Clock Interface 2.16.2. Time-of-Day Interface 2.16.3. TX 2-Step Timestamp Interface 2.16.4. TX 1-Step Timestamp Interface 2.16.5. RX Timestamp Interface 2.16.6. PTP Status Interface 2.16.7. PTP Tile Interface
4. Designing with the IP Core x
4.1. Specifying the IP Core Parameters and Options 4.2. Generated File Structure
4.1. Specifying the IP Core Parameters and Options x
4.1.1. Reference and System PLL Clock for your IP Design
5. Block Description x
5.1. Precision Time Protocol
1. Introduction
2. Interface Overview
3. Parameters
4. Designing with the IP Core
5. Block Description
6. Configuration Registers
7. F-Tile Ethernet Multirate Intel FPGA IP User Guide Archives
8. Document Revision History for the F-Tile Ethernet Multirate Intel FPGA IP User Guide

1.7. F-Tile Ethernet Multirate IP Core Features and Constraints

This section describes features and limitation in the current IP release.
  • The IP only supports symmetric fractures at startup or after DR switching where all ports in a specific configuration must use the same rate and modulation. For example, for 100GE-4 base reconfiguration profile, a valid secondary profile is 2x 50GE-2. An invalid secondary profiles are 1x 50GE-1 and 1x50GE-2 due to modulation mixture. The IP can have multiple profiles with different rates and modulations (NRZ or PAM4), but if the startup profile supports multiple ports, then these ports must be of the same rate and modulation. When switching profiles, the rate and modulation of the selected profiles must be the same.
    Attention: In the 25GE-1 Reconfigurable group for FGT mode, the 25GE profile can reconfigure as a 25GE and 10GE rate. In a multi-port 25GE profile, you can configure a mixture of 10GE and 25GE rates.
  • The MAC-segmented interface is only available for MAC variants.
  • All transceivers in a FGT reconfiguration group must be placed within a FGT QUAD:
    • A reconfiguration group using four transceivers cannot use lanes partially from two different FGT QUADs.
    • A reconfiguration group using eight transceivers must occupy exactly two adjacent FGT QUADs.
  • The dynamic reconfiguration flow must use the same reconfiguration clock for the F-Tile Dynamic Reconfiguration Suite Intel® FPGA IP and all Multirate IP instances targeting a specific F-tile.
  • The IP does not support the system PLL frequency of 322 MHz.
  • All reconfiguration group ports must use the same PMA reference clock.
  • The current release does not support external custom cadence. The custom cadence required for applicable scenarios is generated internally within the Multirate IP core.
  • If Stop TX traffic when link partner sends pause parameter is partially enabled and disabled for some profiles, the dynamic reconfiguration switch fails to program that information into the soft IP where the feature is implemented as a part of work around; hence, you should write into the CSRs to enable/disable this feature after a profile switch is completed.
  • The F-Tile Ethernet Multirate IP does not support 40GE-4 rate with Precision Time Protocol (PTP) enabled.
  • Mixture of PTP and non-PTP profiles is not supported, so there is no run-time DR from PTP enabled to PTP disabled or vice versa.
  • Mixture of PTP with Basic and Advanced accuracy modes is not supported.
  • Mixture of different PTP fingerprint widths is not supported.
  • You must run the PTP flows described in F-Tile Ethernet Intel FPGA Hard IP User Guide.
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