F-Tile Dynamic Reconfiguration Suite Intel® FPGA IP User Guide

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ID 711009
Date 7/08/2024
Public
Document Table of Contents
Document Table of Contents x
1. About the F-Tile Dynamic Reconfiguration Suite Core 2. Interface Overview 3. Parameters 4. Designing with the IP Core 5. Block Description 6. Configuration Registers 7. F-Tile Dynamic Reconfiguration Suite Intel® FPGA IP User Guide Archives 8. Document Revision History for the F-Tile Dynamic Reconfiguration Suite User Guide
1. About the F-Tile Dynamic Reconfiguration Suite Core x
1.1. Features 1.2. Design Considerations 1.3. Device Family Support 1.4. Resource Utilization 1.5. Release Information
2. Interface Overview x
2.1. Clock Signals 2.2. Reset 2.3. Avalon® Memory-Mapped Interface 2.4. Control and Status Interface
4. Designing with the IP Core x
4.1. Generating Dynamic Reconfiguration Design and Configuration Profiles 4.2. Dynamic Reconfiguration QSF Settings 4.3. Dynamic Reconfiguration Using QSF-driven Flow 4.4. Dynamic Reconfiguration Rules 4.5. Hardware States and Configuration Profiles 4.6. Nios® -Based Dynamic Reconfiguration Flow 4.7. Using the Tile Assignment Editor 4.8. Visualizing Dynamic Reconfiguration Group Placement 4.9. Assigning IP_COLOCATE Hierarchy 4.10. Example: Dynamic Reconfiguration with Multirate IP Flow 4.11. Example: Dynamic Reconfiguration Programming Sequence 4.12. Dynamic Reconfiguration Error Recovery Handling 4.13. Determining Profile Numbers 4.14. Master Clock Channel 4.15. Using the IP_RECONFIG_GROUP_PARENT QSF Assignment 4.16. Simulating the IP Core
4.6. Nios® -Based Dynamic Reconfiguration Flow x
4.6.1. Selecting the Nios® Data Memory Size
4.7. Using the Tile Assignment Editor x
4.7.1. Creating QSF Assignments 4.7.2. Generating the IP_Colocate QSF Assignment
4.14. Master Clock Channel x
4.14.1. Selecting the Master Clock Channel
5. Block Description x
5.1. Clocks 5.2. Reset 5.3. Stack Clocking for Fracturability
6. Configuration Registers x
6.1. Dynamic Reconfiguration New Trigger 6.2. Dynamic Reconfiguration Next Profile 0 6.3. Dynamic Reconfiguration Next Profile 1 6.4. Dynamic Reconfiguration Next Profile 2 6.5. Dynamic Reconfiguration Next Profile 3 6.6. Dynamic Reconfiguration Next Profile 4 6.7. Dynamic Reconfiguration Next Profile 5 6.8. Dynamic Reconfiguration Next Profile 6 6.9. Dynamic Reconfiguration Next Profile 7 6.10. Dynamic Reconfiguration Next Profile 8 6.11. Dynamic Reconfiguration Next Profile 9 6.12. Dynamic Reconfiguration Next Profile 10 6.13. Dynamic Reconfiguration Next Profile 11 6.14. Dynamic Reconfiguration Next Profile 12 6.15. Dynamic Reconfiguration Next Profile 13 6.16. Dynamic Reconfiguration Next Profile 14 6.17. Dynamic Reconfiguration Next Profile 15 6.18. Dynamic Reconfiguration Next Profile 16 6.19. Dynamic Reconfiguration Next Profile 17 6.20. Dynamic Reconfiguration Next Profile 18 6.21. Dynamic Reconfiguration Next Profile 19 6.22. Dynamic Reconfiguration Avalon MM Timeout 6.23. Dynamic Reconfiguration TX Channel Reconfiguration 6.24. Dynamic Reconfiguration RX Channel Reconfiguration 6.25. Dynamic Reconfiguration TX Channel in Reset Acknowledgment 6.26. Dynamic Reconfiguration TX Channel out of Reset 6.27. Dynamic Reconfiguration TX Channel Reset Control Init Status 6.28. Dynamic Reconfiguration TX Channel Source Alarm 6.29. Dynamic Reconfiguration RX Channel in Reset Acknowledgment 6.30. Dynamic Reconfiguration RX Channel out of Reset 6.31. Dynamic Reconfiguration RX Channel Reset Control Init Status 6.32. Dynamic Reconfiguration RX Channel Source Alarm 6.33. Dynamic Reconfiguration Local Error Status
1. About the F-Tile Dynamic Reconfiguration Suite Core
2. Interface Overview
3. Parameters
4. Designing with the IP Core
5. Block Description
6. Configuration Registers
7. F-Tile Dynamic Reconfiguration Suite Intel® FPGA IP User Guide Archives
8. Document Revision History for the F-Tile Dynamic Reconfiguration Suite User Guide

4.3. Dynamic Reconfiguration Using QSF-driven Flow

This design example describes a reconfiguration group consisting for the 50G Ethernet Multirate IP core, 25G CPRI Multirate IP core, and the 100G Direct PHY IP.

In addition to the proper RTL connections for this design consisting of an instance of the Reconfiguration Controller Suite IP, the System Clock IP, and the three protocol IPs, the design requires the .qsf assignments shown below:
  • Create a dynamic reconfiguration group for all IPs, including the Multirate IPs:
    set_global_assignment -name IP_RECONFIG_GROUP_TYPE RG_TEST_GP:EXCLUSIVE:CLK_MASTER
set_instance_assignment -name IP_RECONFIG_GROUP RG_TEST_GP -to my_dphy_inst_1|dphy_f_dr_0  

# Derive MR IP group name from QIP file and hpath of every instance to construct child DR group name
set_instance_assignment -name IP_RECONFIG_GROUP_PARENT RG_TEST_GP:my_mr_eth_inst_2|eth_f_dr_0/RG_A  
set_instance_assignment -name IP_RECONFIG_GROUP_PARENT RG_TEST_GP:my_mr_cpri_inst_3|cpriphy_mr_f_0/RG_A
  • Specify startup instance for the dynamic reconfiguration group:
    set_instance_assignment -name IP_RECONFIG_GROUP_STARTUP_INSTANCE OFF \
–to my_mr_eth_inst_2|eth_f_dr_0|U_base_profile|eth_f_0

set_instance_assignment -name IP_RECONFIG_GROUP_STARTUP_INSTANCE OFF \
–to my_mr_cpri_inst_3|cpriphy_mr_f_0|profile_0|cpriphy_ftile_0

set_instance_assignment -name IP_RECONFIG_GROUP_STARTUP_INSTANCE ON \
–to my_dphy_inst_1|dphy_f_dr_0 |profile_0|dphy_ftile_0
  • Bind each member IP of the dynamic reconfiguration group to a reconfiguration controller:
    set_instance_assignment -name IP_COLOCATE F_TILE \
-from dr_ctrl_inst_1|dr_f_0 -to my_dphy_inst_1|dphy_f_dr_0

set_instance_assignment -name IP_COLOCATE F_TILE \
-from dr_ctrl_inst_1|dr_f_0 -to my_mr_eth_inst_2|eth_f_dr_0 

set_instance_assignment -name IP_COLOCATE F_TILE \
-from dr_ctrl_inst_1|dr_f_0 -to my_mr_cpri_inst_3|cpriphy_mr_f_0
QSF assignments can also be used to modify the PMA analog parameters for your protocol IP on a per-profile basis. Examples of such assignments are shown below for a 2-lane DPHY MRIP variant with 2 profiles: 
set_instance_assignment -name HSSI_PARAMETER "vsr_mode=VSR_MODE_DISABLE" -to q1_inst|dut|directphy_f_dr_0|U_base_profile|directphy_f_0|dphy_hip_inst|
persystem[0].perxcvr[1].fgt.rx_ux.x_bb_f_ux_rx -entity dphy_f_dr_intc_top

set_instance_assignment -name HSSI_PARAMETER "vsr_mode=VSR_MODE_DISABLE" -to 
q1_inst|dut|directphy_f_dr_0|U_base_profile|directphy_f_0|dphy_hip_inst|
persystem[0].perxcvr[0].fgt.rx_ux.x_bb_f_ux_rx -entity dphy_f_dr_intc_top

set_instance_assignment -name HSSI_PARAMETER "vsr_mode=VSR_MODE_HIGH_LOSS" -to 
q1_inst|dut|directphy_f_dr_0|U_sec_profile1|sec_profile_1|dphy_hip_inst|
persystem[0].perxcvr[0].fgt.rx_ux.x_bb_f_ux_rx -entity dphy_f_dr_intc_top

set_instance_assignment -name HSSI_PARAMETER "vsr_mode=VSR_MODE_HIGH_LOSS" -to 
q1_inst|dut|directphy_f_dr_0|U_sec_profile1|sec_profile_1|dphy_hip_inst|
persystem[0].perxcvr[1].fgt.rx_ux.x_bb_f_ux_rx -entity dphy_f_dr_intc_top

Note that the protocol IPs also contain Analog parameters tabs, which can be used to implement per-profile analog settings. Be aware that the QSF assignments take precedence over any GUI settings used in the protocol IPs.

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