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1. HDMI Intel® FPGA IP Design Example Quick Start Guide for Agilex™ 7 F-Tile Devices
2. HDMI 2.1 Design Example (Support FRL = 1, Enable Active Video Protocol = None)
3. HDMI 2.1 Design Example with AXI4-stream Interface Enabled (Support FRL =1, Enable Active Video Protocol = AXIS-VVP Full)
4. Document Revision History for the F-Tile HDMI Intel® FPGA IP Design Example User Guide
2.1. Design Features
2.2. Hardware and Software Requirements
2.3. HDMI 2.1 RX-TX Retransmit Design Block Diagram
2.4. Design Parameters
2.5. Design Components
2.6. Design Software Flow
2.7. Clocking Scheme
2.8. Interface Signals
2.9. Hardware Setup
2.10. Simulation Testbench
2.11. Debugging Features
3.7.1. HDMI 2.1 RX-TX Retransmit Design without Video Frame Buffer (Enable Active Video Protocol = AXIS-VVP Full, Video In and Out Use the Same Clock = ON)
3.7.2. HDMI 2.1 RX-TX Retransmit Design with Video Frame Buffer (Enable Active Video Protocol = AXIS-VVP Full, Video In and Out Use the Same = OFF)
3.7.3. Clock Details
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1.3. Simulating the Design
The HDMI testbench simulates a serial loopback design from a TX instance to an RX instance. Internal video pattern generator, audio sample generator, sideband data generator, and auxiliary data generator modules drive the HDMI TX instance and the serial output from the TX instance connects to the RX instance in the testbench.
Note: HDMI simulation is not supported when the Include I2C Master/Slave option is enabled in the IP tab.
Figure 4. Design Simulation Flow
- Go to the desired simulation folder.
- Run the simulation script for the supported simulator of your choice. The script compiles and runs the testbench in the simulator.
- Analyze the results.
Table 5. Steps to Run Simulation Simulator Working Directory Instructions Riviera-PRO* /simulation/aldec In the command line, typevsim -c -do aldec.do
ModelSim* /simulation/mentor In the command line, typevsim -c -do mentor.do
VCS* /simulation/synopsys/vcs In the command line, typesource vcs_sim.sh
VCS* MX /simulation/synopsys/vcsmx In the command line, typesource vcsmx_sim.sh
Xcelium* Parallel /simulation/xcelium In the command line, type source xcelium_sim.sh
A successful simulation ends with the following message:# SYMBOLS_PER_CLOCK = 2 # VIC = 4 # BPP = 0 # AUDIO_FREQUENCY (kHz) = 48 # AUDIO_CHANNEL = 8 # Simulation pass