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1. About the F-Tile JESD204C Intel® FPGA IP User Guide
2. Overview of the F-Tile JESD204C Intel® FPGA IP
3. Functional Description
4. Getting Started
5. Designing with the F-Tile JESD204C Intel® FPGA IP
6. F-Tile JESD204C Intel® FPGA IP Parameters
7. Interface Signals
8. Control and Status Registers
9. F-Tile JESD204C Intel® FPGA IP User Guide Archives
10. Document Revision History for the F-Tile JESD204C Intel® FPGA IP User Guide
4.1. Installing and Licensing Intel® FPGA IP Cores
4.2. Intel® FPGA IP Evaluation Mode
4.3. IP Catalog and Parameter Editor
4.4. F-Tile JESD204C IP Component Files
4.5. Creating a New Quartus® Prime Project
4.6. Parameterizing and Generating the IP
4.7. Compiling the F-Tile JESD204C IP Design
4.8. Programming an FPGA Device
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5.7.1. RBD Tuning Mechanism
The following figures focus on the RBD tuning mechanism and how RBD count and RBD offset are used to tune the deterministic latency.
Figure 14. RBD Tuning
Figure 15. RBD Tuning (Power Cycle Variation)
Figure 16. RBD Tuning (Utilizing RBD Offset for Early Release)
Figure 17. RBD Tuning (LEMC Slip)
Figure 18. RBD Tuning (LEMC Slip, if RBD Tuning Using RBD Offset is Not Used)
Figure 19. RBD Tuning (RBD Offset Tuning Legal Range)
Figure 20. RBD Tuning (RBD Tuning when RBD Count Arrival Shifts Before and After LEMC in Multi-Reset)
Figure 21. RBD Tuning (RBD Offset Tuning - Legal Range)
Figure 22. RBD Tuning (RBD Offset Tuning using RBD Offset - Legal Range)
The following figure shows the RBD tuning in actual numerical representative used in the F-Tile JESD204C RX IP core.
Figure 23. RBD Tuning (RBD Offset using Numerical Representative for LEMC = 15 Down to 0)