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Ixiasoft
Visible to Intel only — GUID: qvv1523205769746
Ixiasoft
2.1. Quick Start Guide
The E-Tile Ethernet IP for Agilex™ 7 FPGA core for Agilex™ 7 devices provides a simulation testbench and a hardware design example that supports compilation and hardware testing. When you generate the design example, the parameter editor automatically creates the files necessary to simulate, compile, and test the design in hardware.
In addition, Intel Agilex® 7 provides a compilation-only example project that you can use to quickly estimate IP core area and timing.
Data Rate | Variant | Simulation | Compilation-Only Project | Hardware Design Example |
---|---|---|---|---|
10GE | Single or multi channels Media Access Controller (MAC) + Physical Coding Sublayer (PCS) with optional 1588 Precision Time Protocol (PTP) | √ | √ | √ |
Single channel PCS | √ | √ | √ | |
Single channel Optical Transport Network (OTN) | √ | √ | X | |
Single channel Flexible Ethernet (FlexE) | √ | √ | X | |
Single or multi channels custom PCS | √ | √ | √ | |
25GE | Single or multi channels MAC + PCS with optional RS-FEC and optional PTP |
√ | √ | √ |
Single channel PCS with optional RS-FEC | √ | √ | √ | |
Single channel OTN with optional RS-FEC | √ | √ | X | |
Single channel FlexE with optional RS-FEC | √ | √ | X | |
Single or multi channels custom PCS with optional RS-FEC | √ | √ | √ | |
100GE | MAC+ PCS with optional:
|
√ | √ | √ |
MAC+PCS with (544, 514) RS-FEC | √ | √ | √ | |
PCS with optional (528,514) or (544, 514) RS-FEC | √ | √ | √ | |
OTN with optional (528,514) or (544, 514) RS-FEC | √ | √ | X | |
FlexE with optional (528,514) or (544, 514) RS-FEC | √ | √ | X |
Section Content
Directory Structure
Generating the Design
Simulating the E-tile Ethernet IP for Intel Agilex 7 FPGA Design Example Testbench
Compiling the Compilation-Only Project
Compiling and Configuring the Design Example in Hardware
Testing the E-tile Ethernet IP for Intel Agilex 7 FPGA Hardware Design Example