Visible to Intel only — GUID: yqq1553224906727
Ixiasoft
2.1.1. Directory Structure
2.1.2. Generating the Design
2.1.3. Simulating the E-tile Ethernet IP for Intel Agilex® 7 FPGA Design Example Testbench
2.1.4. Compiling the Compilation-Only Project
2.1.5. Compiling and Configuring the Design Example in Hardware
2.1.6. Testing the E-tile Ethernet IP for Intel Agilex® 7 FPGA Hardware Design Example
2.2.1.1. Non-PTP 10GE/25GE MAC+PCS with Optional RS-FEC Simulation Design Example
2.2.1.2. PTP 10GE/25GE MAC+PCS with Optional RS-FEC Simulation Design Example
2.2.1.3. 10GE/25GE PCS Only, OTN, or FlexE with Optional RS-FEC Simulation Design Example
2.2.1.4. 10GE/25GE Custom PCS with Optional RS-FEC Simulation Design Example
2.3.1. Simulation Design Examples
2.3.2. Hardware Design Examples
2.3.3. 100GE MAC+PCS with Optional RS-FEC Design Example Interface Signals
2.3.4. 100GE PCS with Optional RS-FEC Design Example Interface Signals
2.3.5. 100GE MAC+PCS with Optional RS-FEC Design Example Registers
2.3.6. 100GE PCS with Optional RS-FEC Design Example Registers
2.3.1.1. Non-PTP E-tile Ethernet IP for Intel Agilex® 7 FPGA 100GE MAC+PCS with Optional RS-FEC Simulation Design Example
2.3.1.2. E-tile Ethernet IP for Intel Agilex® 7 FPGA 100GE MAC+PCS with Optional RS-FEC and PTP Simulation Design Example
2.3.1.3. E-tile Ethernet IP for Intel Agilex® 7 FPGA 100GE PCS Only with Optional RS-FEC Simulation Design Example
2.3.1.4. E-tile Ethernet IP for Intel Agilex® 7 FPGA 100GE OTN with Optional RS-FEC Simulation Design Example
2.3.1.5. E-tile Ethernet IP for Intel Agilex® 7 FPGA 100GE FlexE with Optional RS-FEC Simulation Design Example
2.3.2.1. 100GE MAC+PCS with Optional RS-FEC and PMA Adaptation Flow Hardware Design Example Components
2.3.2.2. 100GE MAC+PCS with Optional RS-FEC and PTP Hardware Design Example
2.3.2.3. 100GE PCS with Optional RS-FEC Hardware Design Example Components
2.3.2.4. Ethernet Adaptation Flow for 100G (CAUI-2) PAM4 <---> 100G (CAUI-4) NRZ Dynamic Reconfiguration Design Example
3.1.1. Hardware and Software Requirements
3.1.2. Generating the Design
3.1.3. Directory Structure
3.1.4. Simulating the Design Example Testbench
3.1.5. Compiling the Compilation-Only Project
3.1.6. Compiling and Configuring the Design Example in Hardware
3.1.7. Testing the E-tile CPRI PHY Intel® FPGA IP Hardware Design Example
4.1. Quick Start Guide
4.2. 10G/25G Ethernet Dynamic Reconfiguration Design Examples
4.3. 25G Ethernet to CPRI Dynamic Reconfiguration Design Example
4.4. CPRI Dynamic Reconfiguration Design Examples
4.5. 100G Ethernet Dynamic Reconfiguration Design Example
4.6. Document Revision History for the E-Tile Dynamic Reconfiguration Design Example
4.5.1. Functional Description
4.5.2. Testing the 100G Ethernet Dynamic Reconfiguration Hardware Design Example
4.5.3. Simulation Design Examples
4.5.4. 100GE DR Hardware Design Examples
4.5.5. 100G Ethernet Dynamic Reconfiguration Design Example Interface Signals
4.5.6. 100G Ethernet Dynamic Reconfiguration Examples Registers
4.5.7. Steps to Enable FEC
4.5.8. Steps to Disable FEC
Visible to Intel only — GUID: yqq1553224906727
Ixiasoft
4.1.3.2. Generating New HEX File Using Eclipse-based Ashling RiscFree IDE Tool
Use Eclipse-based Ashling Riscfree IDE tool to generate HEX file instead of running the script generate_hex_script.sh.
- In the <design_example_dir>/software/dynamic_reconfiguration_sim folder, execute the following commands:
- Execute the command niosv-bsp -c --quartus-project=../../hardware_test_design/alt_ehipc3.qpf --qsys=../../hardware_test_design/nios_system.qsys --type=hal etile_dr_cpu_bsp/settings.bsp to generate the BSP files.
- Execute the command niosv-app --bsp-dir=etile_dr_cpu_bsp --app-dir=etile_dr_cpu_app --srcs=. --elfname=etile_dr_cpu.elf to generate the user application CMakeLists.txt.
- Run the Eclipse-based Ashling Riscfree IDE Tool launcher.
- Create a new workspace when the Workspace Launcher window prompt appears.
- Click Launch to open the workspace.
- In the Eclipse-based Ashling Riscfree IDE Tool window, select File > New > Project. A New Project window appears.
- Choose C/C++ > C/C++ Project > C++ Managed Build.
- For the Project name, specify your desired project name. This example uses dynamic_reconfiguration_simulation.
- For project type, select CMake driven > Empty Project. For Toolchains, select CMake driven.
- Click Finish. The CMake driven application is added to the Project Explorer.
- Uncheck Use default location. Navigate to <example_design_dir>/software/dynamic_reconfiguration_sim/etile_dr_cpu_app to locate the CMakeLists.txt in the NIOS V application project.
- On the Project Explorer view, right-click the project and select Build Project. Ensure the etile_dr_cpu.elf file is generated in the <design_example_dir>/software/dynamic_reconfiguration_sim/etile_dr_cpu_app/build/Debug directory.
- Do the following to generate a Hex file:
- Go to <design_example_dir>/software/ dynamic_reconfiguration_sim.
- Run the command elf2hex etile_dr_cpu_app/build/Debug/etile_dr_cpu.elf -o nios_system_oc_mem2_0 _onchip_memory2_0.hex -b 0x04000000 -r 4 -w 32 -e 0x0407ffff.
Follow these steps to simulate the testbench:
- Open the <simulator_name>_files.tcl script in the <design_example_dir>/example_testbench/setup_scripts/common directory.
- Edit the TCL script to change the existing nios_system_oc_mem2_0_onchip_memory2_0.hex file directory to the new HEX file generated from the Eclipse-based Ashling RiscFree IDE Tool.
For example, change the following line in the TCL script from:
lappend memory_files "[normalize_path "$QSYS_SIMDIR/../<design_example_dir>/hardware_test_design/ip/nios_system/nios_system_oc_mem2_0/altera_avalon_onchip_memory2_191/sim/nios_system_oc_mem2_0_onchip_memory2_0.hex"]"
tolappend memory_files "[normalize_path "$QSYS_SIMDIR/../<design_example_dir>/hardware_test_design/software/dynamic_reconfiguration_sim/nios_system_oc_mem2_0_onchip_memory2_0.hex"]"
- Using the supported simulator of your choice, change to the testbench simulation directory to <design_example_dir>/example_testbench/ <simulator_name>.
- Run the simulation script for the simulator. The script compiles and runs the testbench in the simulator. Refer to the Steps to Simulate the Testbench table.
- Analyze the results. The successful testbench performs the DR operations, sends and transmits packets for each DR operation, and displays "Nios has completed its transactions" and "Simulation PASSED" after completing the simulation.
Note: For Nios® V-based testbench, the simulation runs for more than 5 hours.
Related Information