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2.1.1. Directory Structure
2.1.2. Generating the Design
2.1.3. Simulating the E-tile Ethernet IP for Intel Agilex® 7 FPGA Design Example Testbench
2.1.4. Compiling the Compilation-Only Project
2.1.5. Compiling and Configuring the Design Example in Hardware
2.1.6. Testing the E-tile Ethernet IP for Intel Agilex® 7 FPGA Hardware Design Example
2.2.1.1. Non-PTP 10GE/25GE MAC+PCS with Optional RS-FEC Simulation Design Example
2.2.1.2. PTP 10GE/25GE MAC+PCS with Optional RS-FEC Simulation Design Example
2.2.1.3. 10GE/25GE PCS Only, OTN, or FlexE with Optional RS-FEC Simulation Design Example
2.2.1.4. 10GE/25GE Custom PCS with Optional RS-FEC Simulation Design Example
2.3.1. Simulation Design Examples
2.3.2. Hardware Design Examples
2.3.3. 100GE MAC+PCS with Optional RS-FEC Design Example Interface Signals
2.3.4. 100GE PCS with Optional RS-FEC Design Example Interface Signals
2.3.5. 100GE MAC+PCS with Optional RS-FEC Design Example Registers
2.3.6. 100GE PCS with Optional RS-FEC Design Example Registers
2.3.1.1. Non-PTP E-tile Ethernet IP for Intel Agilex® 7 FPGA 100GE MAC+PCS with Optional RS-FEC Simulation Design Example
2.3.1.2. E-tile Ethernet IP for Intel Agilex® 7 FPGA 100GE MAC+PCS with Optional RS-FEC and PTP Simulation Design Example
2.3.1.3. E-tile Ethernet IP for Intel Agilex® 7 FPGA 100GE PCS Only with Optional RS-FEC Simulation Design Example
2.3.1.4. E-tile Ethernet IP for Intel Agilex® 7 FPGA 100GE OTN with Optional RS-FEC Simulation Design Example
2.3.1.5. E-tile Ethernet IP for Intel Agilex® 7 FPGA 100GE FlexE with Optional RS-FEC Simulation Design Example
2.3.2.1. 100GE MAC+PCS with Optional RS-FEC and PMA Adaptation Flow Hardware Design Example Components
2.3.2.2. 100GE MAC+PCS with Optional RS-FEC and PTP Hardware Design Example
2.3.2.3. 100GE PCS with Optional RS-FEC Hardware Design Example Components
2.3.2.4. Ethernet Adaptation Flow for 100G (CAUI-2) PAM4 <---> 100G (CAUI-4) NRZ Dynamic Reconfiguration Design Example
3.1.1. Hardware and Software Requirements
3.1.2. Generating the Design
3.1.3. Directory Structure
3.1.4. Simulating the Design Example Testbench
3.1.5. Compiling the Compilation-Only Project
3.1.6. Compiling and Configuring the Design Example in Hardware
3.1.7. Testing the E-tile CPRI PHY Intel® FPGA IP Hardware Design Example
4.1. Quick Start Guide
4.2. 10G/25G Ethernet Dynamic Reconfiguration Design Examples
4.3. 25G Ethernet to CPRI Dynamic Reconfiguration Design Example
4.4. CPRI Dynamic Reconfiguration Design Examples
4.5. 100G Ethernet Dynamic Reconfiguration Design Example
4.6. Document Revision History for the E-Tile Dynamic Reconfiguration Design Example
4.5.1. Functional Description
4.5.2. Testing the 100G Ethernet Dynamic Reconfiguration Hardware Design Example
4.5.3. Simulation Design Examples
4.5.4. 100GE DR Hardware Design Examples
4.5.5. 100G Ethernet Dynamic Reconfiguration Design Example Interface Signals
4.5.6. 100G Ethernet Dynamic Reconfiguration Examples Registers
4.5.7. Steps to Enable FEC
4.5.8. Steps to Disable FEC
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2.3.2.4. Ethernet Adaptation Flow for 100G (CAUI-2) PAM4 <---> 100G (CAUI-4) NRZ Dynamic Reconfiguration Design Example
There are two new Dynamic Reconfiguration transitions:
- 100G NRZ with RSFEC [KR-FEC (528,514)] / without RSFEC <--> 100G NRZ with RSFEC [KP-FEC (544,514)]
- 100G NRZ with RSFEC [KR-FEC (528,514)] / without RSFEC <--> 100G PAM4 with RSFEC [KP-FEC (544,514)]
The following figure provides an overview of the Dynamic Reconfiguration transitions.
Figure 21. Dynamic Reconfiguration Transitions
To achieve the dynamic reconfiguration modes listed above, the 100G Dynamic Reconfiguration Design Example has been enhanced and the required modifications are described below:
- 100G Ethernet IP:
- The parameter DR_100G_NRZ_PAM4 needs to be set in the IP.
- This is because the power up mode for the 100G Ethernet IP is in 100G NRZ mode. In this power up mode, the parallel clock is running at 402.8 MHz. When the Ethernet IP is configured to 100G PAM4 mode after performing dynamic reconfiguration, the parallel clock runs at a higher frequency which is 415 MHz.
- Therefore, to ensure Quartus® Prime Timing Analyzer covers and analyzes the timing performance when the design is running at either NRZ mode or PAM4 mode, two timing profiles need to be available for the proper analysis to be performed. When this parameter is set, observe two timing profile clocks reported in Timing Analyzer, whereby:
- timing profile 0 is for power-up mode (100G NRZ) - 402.8MHz
- timing profile 1 for 100G PAM4 mode – 415MHz
- C-code files – dynamic_reconfig.cpp and dynamic_reconfig.h—C-codes to enable PAM4 and NRZ [KP-FEC (544,514)] Dynamic Reconfiguration transition support.
- Hex file—Hex file generated for design simulation and hardware run.