E-Tile Hard IP Agilex™ 7 Design Example User Guide: Ethernet, E-tile CPRI PHY and Dynamic Reconfiguration

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ID 683860
Date 4/30/2024
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Document Table of Contents
Document Table of Contents x
1. About E-tile Hard IP Agilex™ 7 Design Example User Guide 2. E-Tile Ethernet IP for Agilex™ 7 FPGA Design Example 3. E-tile CPRI PHY Intel® FPGA IP Design Example 4. E-Tile Dynamic Reconfiguration Design Example 5. E-tile Hard IP Agilex™ 7 Design Examples User Guide Archives
2. E-Tile Ethernet IP for Agilex™ 7 FPGA Design Example x
2.1. Quick Start Guide 2.2. 10GE/25GE with Optional RS-FEC Design Examples 2.3. 100GE with Optional RS-FEC Design Example 2.4. Ethernet Toolkit Overview 2.5. Document Revision History for the E-tile Hard IP for Ethernet Agilex™ 7 FPGA IP Design Example User Guide
2.1. Quick Start Guide x
2.1.1. Directory Structure 2.1.2. Generating the Design 2.1.3. Simulating the E-tile Ethernet IP for Intel Agilex® 7 FPGA Design Example Testbench 2.1.4. Compiling the Compilation-Only Project 2.1.5. Compiling and Configuring the Design Example in Hardware 2.1.6. Testing the E-tile Ethernet IP for Intel Agilex® 7 FPGA Hardware Design Example
2.1.3. Simulating the E-tile Ethernet IP for Intel Agilex® 7 FPGA Design Example Testbench x
2.1.3.1. Fast Sim Model for E-tile Ethernet IP for Intel Agilex® 7 FPGA
2.1.6. Testing the E-tile Ethernet IP for Intel Agilex® 7 FPGA Hardware Design Example x
2.1.6.1. 10GE/25GE Design Example 2.1.6.2. 100GE MAC+PCS with Optional (528,514) RS-FEC or (544,514) RS-FEC and Adaptation Flow Hardware Design Example 2.1.6.3. 100GE PCS Only with Optional (528,514) RS-FEC or (544,514) RS-FEC, and Optional PTP Hardware Design Example
2.2. 10GE/25GE with Optional RS-FEC Design Examples x
2.2.1. Simulation Design Examples 2.2.2. Hardware Design Examples 2.2.3. 10GE/25GE Design Example Interface Signals 2.2.4. 10GE/25GE Design Examples Registers
2.2.1. Simulation Design Examples x
2.2.1.1. Non-PTP 10GE/25GE MAC+PCS with Optional RS-FEC Simulation Design Example 2.2.1.2. PTP 10GE/25GE MAC+PCS with Optional RS-FEC Simulation Design Example 2.2.1.3. 10GE/25GE PCS Only, OTN, or FlexE with Optional RS-FEC Simulation Design Example 2.2.1.4. 10GE/25GE Custom PCS with Optional RS-FEC Simulation Design Example
2.2.2. Hardware Design Examples x
2.2.2.1. 10GE/25GE MAC+PCS with Optional RS-FEC and PTP Hardware Design Example Components 2.2.2.2. 10GE/25GE PCS Only with Optional RS-FEC Hardware Design Example Components 2.2.2.3. 10GE/25GE Custom PCS with Optional RS-FEC Hardware Design Example
2.3. 100GE with Optional RS-FEC Design Example x
2.3.1. Simulation Design Examples 2.3.2. Hardware Design Examples 2.3.3. 100GE MAC+PCS with Optional RS-FEC Design Example Interface Signals 2.3.4. 100GE PCS with Optional RS-FEC Design Example Interface Signals 2.3.5. 100GE MAC+PCS with Optional RS-FEC Design Example Registers 2.3.6. 100GE PCS with Optional RS-FEC Design Example Registers
2.3.1. Simulation Design Examples x
2.3.1.1. Non-PTP E-tile Ethernet IP for Intel Agilex® 7 FPGA 100GE MAC+PCS with Optional RS-FEC Simulation Design Example 2.3.1.2. E-tile Ethernet IP for Intel Agilex® 7 FPGA 100GE MAC+PCS with Optional RS-FEC and PTP Simulation Design Example 2.3.1.3. E-tile Ethernet IP for Intel Agilex® 7 FPGA 100GE PCS Only with Optional RS-FEC Simulation Design Example 2.3.1.4. E-tile Ethernet IP for Intel Agilex® 7 FPGA 100GE OTN with Optional RS-FEC Simulation Design Example 2.3.1.5. E-tile Ethernet IP for Intel Agilex® 7 FPGA 100GE FlexE with Optional RS-FEC Simulation Design Example
2.3.2. Hardware Design Examples x
2.3.2.1. 100GE MAC+PCS with Optional RS-FEC and PMA Adaptation Flow Hardware Design Example Components 2.3.2.2. 100GE MAC+PCS with Optional RS-FEC and PTP Hardware Design Example 2.3.2.3. 100GE PCS with Optional RS-FEC Hardware Design Example Components 2.3.2.4. Ethernet Adaptation Flow for 100G (CAUI-2) PAM4 <---> 100G (CAUI-4) NRZ Dynamic Reconfiguration Design Example
2.4. Ethernet Toolkit Overview x
2.4.1. Features
3. E-tile CPRI PHY Intel® FPGA IP Design Example x
3.1. E-tile CPRI PHY Intel® FPGA IP Quick Start Guide 3.2. E-tile CPRI PHY Design Example Description 3.3. Document Revision History for the E-tile CPRI PHY Intel® FPGA IP Design Example User Guide
3.1. E-tile CPRI PHY Intel® FPGA IP Quick Start Guide x
3.1.1. Hardware and Software Requirements 3.1.2. Generating the Design 3.1.3. Directory Structure 3.1.4. Simulating the Design Example Testbench 3.1.5. Compiling the Compilation-Only Project 3.1.6. Compiling and Configuring the Design Example in Hardware 3.1.7. Testing the E-tile CPRI PHY Intel® FPGA IP Hardware Design Example
3.2. E-tile CPRI PHY Design Example Description x
3.2.1. Features 3.2.2. Simulation Design Example 3.2.3. Hardware Design Example 3.2.4. Interface Signals 3.2.5. Design Example Register Map for Reconfiguration
4. E-Tile Dynamic Reconfiguration Design Example x
4.1. Quick Start Guide 4.2. 10G/25G Ethernet Dynamic Reconfiguration Design Examples 4.3. 25G Ethernet to CPRI Dynamic Reconfiguration Design Example 4.4. CPRI Dynamic Reconfiguration Design Examples 4.5. 100G Ethernet Dynamic Reconfiguration Design Example 4.6. Document Revision History for the E-Tile Dynamic Reconfiguration Design Example
4.1. Quick Start Guide x
4.1.1. Directory Structure 4.1.2. Generating the Design 4.1.3. Simulating the E-Tile Dynamic Reconfiguration Design Example Testbench 4.1.4. Compiling and Configuring the Design Example in Hardware 4.1.5. Testing the E-Tile Dynamic Reconfiguration Hardware Design Example
4.1.2. Generating the Design x
4.1.2.1. Design Example Parameters
4.1.3. Simulating the E-Tile Dynamic Reconfiguration Design Example Testbench x
4.1.3.1. Running the Simulation 4.1.3.2. Generating New HEX File Using Eclipse-based Ashling RiscFree IDE Tool 4.1.3.3. Performing the Link Initialization
4.1.5. Testing the E-Tile Dynamic Reconfiguration Hardware Design Example x
4.1.5.1. Running the Design Example in Hardware 4.1.5.2. Power Management Setting for Agilex™ 7 Transceiver Signal Integrity Development Kit
4.2. 10G/25G Ethernet Dynamic Reconfiguration Design Examples x
4.2.1. Functional Description 4.2.2. Simulation Design Examples 4.2.3. Hardware Design Examples 4.2.4. 10GE/25GE Design Example Interface Signals 4.2.5. 10GE/25GE Design Examples Registers 4.2.6. Dynamic Reconfiguration Flow for 25GbE PTP FEC to 25GbE PTP Non-FEC
4.2.1. Functional Description x
4.2.1.1. Clocking Scheme
4.2.2. Simulation Design Examples x
4.2.2.1. 10GE/25GE MAC+PCS with RS-FEC and PTP Simulation Dynamic Reconfiguration Design Example Components 4.2.2.2. 10GE/25GE MAC+PCS with RS-FEC Simulation Dynamic Reconfiguration Design Example Components
4.2.3. Hardware Design Examples x
4.2.3.1. 10GE/25GE MAC+PCS with RS-FEC and PTP Hardware Dynamic Reconfiguration Design Example Components 4.2.3.2. 10GE/25GE MAC+PCS with RS-FEC Hardware Dynamic Reconfiguration Design Example Components
4.3. 25G Ethernet to CPRI Dynamic Reconfiguration Design Example x
4.3.1. Functional Description 4.3.2. Simulation Design Examples 4.3.3. Hardware Design Examples 4.3.4. 25G Ethernet to CPRI Design Example Interface Signals 4.3.5. 25G Ethernet to CPRI Design Examples Registers 4.3.6. Dynamic Reconfiguration Flow for 25GbE PTP FEC to 24G CPRI FEC
4.3.1. Functional Description x
4.3.1.1. Clocking Scheme 4.3.1.2. Reset
4.3.2. Simulation Design Examples x
4.3.2.1. 25GE MAC+PCS with RS-FEC and PTP to CPRI Simulation Dynamic Reconfiguration Design Example Components
4.3.3. Hardware Design Examples x
4.3.3.1. 25GE MAC+PCS with RS-FEC and PTP to CPRI Hardware Dynamic Reconfiguration Design Example Components
4.4. CPRI Dynamic Reconfiguration Design Examples x
4.4.1. Functional Description 4.4.2. Simulation Design Examples 4.4.3. Hardware Design Examples 4.4.4. CPRI Design Example Interface Signals 4.4.5. CPRI Design Example Registers 4.4.6. Dynamic Reconfiguration Flow for 24G CPRI FEC to 24G CPRI Non-FEC
4.4.1. Functional Description x
4.4.1.1. Clocking Scheme
4.4.2. Simulation Design Examples x
4.4.2.1. 24G CPRI PHY with RS-FEC Simulation Dynamic Reconfiguration Design Example Components 4.4.2.2. 9.8G CPRI PHY Simulation Dynamic Reconfiguration Design Example Components
4.4.3. Hardware Design Examples x
4.4.3.1. CPRI PHY with RS-FEC Hardware Dynamic Reconfiguration Design Example Components
4.5. 100G Ethernet Dynamic Reconfiguration Design Example x
4.5.1. Functional Description 4.5.2. Testing the 100G Ethernet Dynamic Reconfiguration Hardware Design Example 4.5.3. Simulation Design Examples 4.5.4. 100GE DR Hardware Design Examples 4.5.5. 100G Ethernet Dynamic Reconfiguration Design Example Interface Signals 4.5.6. 100G Ethernet Dynamic Reconfiguration Examples Registers 4.5.7. Steps to Enable FEC 4.5.8. Steps to Disable FEC
4.5.2. Testing the 100G Ethernet Dynamic Reconfiguration Hardware Design Example x
4.5.2.1. Dynamic Reconfiguration Flow in 100G Ethernet Dynamic Reconfiguration Example Design
4.5.3. Simulation Design Examples x
4.5.3.1. 100GE MAC+PCS with Optional RS-FEC Dynamic Reconfiguration Simulation Design Example 4.5.3.2. Simulating the E-tile Ethernet IP for Intel Agilex® 7 FPGA Design Example Testbench
4.5.4. 100GE DR Hardware Design Examples x
4.5.4.1. 100GE MAC+PCS with Optional RS-FEC Dynamic Reconfiguration Hardware Design Example Components
4.5.7. Steps to Enable FEC x
4.5.7.1. Configuring for 100G NRZ with RSFEC [KR-FEC (528,514)] 4.5.7.2. Configuring for 100G NRZ with RSFEC [KP-FEC (544,514)] 4.5.7.3. Configuring for 100G PAM4 with RSFEC [KP-FEC (544,514)]
1. About E-tile Hard IP Agilex™ 7 Design Example User Guide
2. E-Tile Ethernet IP for Agilex™ 7 FPGA Design Example
3. E-tile CPRI PHY Intel® FPGA IP Design Example
4. E-Tile Dynamic Reconfiguration Design Example
5. E-tile Hard IP Agilex™ 7 Design Examples User Guide Archives

4.5.2.1. Dynamic Reconfiguration Flow in 100G Ethernet Dynamic Reconfiguration Example Design

The following provides a general sequential flow for the dynamic reconfiguration transition that takes place within this 100G Ethernet Dynamic Reconfiguration design. When a dynamic reconfiguration transition is triggered through the run_test_dr_sw procedure, it executes the underlying dr_calib_switch procedure with the following sequential flow:

  1. Disable Serdes (through PMA attribute code 0x0001). For more information, refer to the E-Tile Transceiver PHY User Guide .
  2. Write 0x6 to Ethernet register 0x310 to assert TX and RX soft reset signals.
  3. Perform PMA Analog Reset. For more information, refer to the E-Tile Transceiver PHY User Guide.
  4. To load initial PMA configuration, write 0x01 to transceiver register 0x91 for every transceiver channel.
  5. Perform dynamic reconfiguration transition based on the arguments passed in through the run_test_dr_sw function. The function arguments determines the values of the dynamic reconfiguration registers. With that, the firmware processes the register space modifications accordingly for the Ethernet, Transceiver and RS-FEC configuration register space.
  6. Enable Serdes (through PMA attribute code 0x0001). For more information, refer to the E-Tile Transceiver PHY User Guide.
  7. Perform dynamic reconfiguration reset (assert and de-assert) through dynamic reconfiguration register 0xE.
  8. Write 0x6 to Ethernet register 0x310 to continue asserting RX soft reset signals.
  9. Enable internal serial loopback.
  10. Trigger PMA adaptation by enabling initial adaptation, check initial adaptation.
  11. Write 0x0 to Ethernet register 0x310 to release TX and RX soft reset signals.

To learn more about the modification performed by the firmware on the Ethernet, Transceiver and RS-FEC registers for various modes, refer to the dynamic_reconfig.cpp file generated in the IP folder.

After you compile the 100G Ethernet E-Tile Dynamic Reconfiguration Design Example and configure it on your device, you can use the procedures to program the IP core.

Table 44.  100G Ethernet Dynamic Reconfiguration Hardware Design Example Functions
Command Setting Description
start_random_pkt_gen_4ch

Starts the packet generator in a random size mode for all four channel lanes.

Example: %start_random_pkt_gen_4ch

stop_pkt_gen_4ch

Immediately stops the packet generator for all four channel lanes.

chkmac_stats $ch

Checks the mac stats counter for the specified channel.

Example:
  • In 100GE mode: %chkmac_stats
  • In 25GE mode: %chkmac_stats 2 for lane 2
run_test_dr

Switches between all available modes and performs the traffic test for each reconfiguration. In 25GE mode, performs four traffic tests, one per each lane.

run_test_dr_sw $elb $mode_curr $mode_target
Switches to a specified mode and performs the traffic test in a loopback mode. 
$mode_target options:
  • 100G_rsfec
  • 100G_kpfec 6
  • 100G_rsfec_544 6
  • 100G_nofec
  • 4x25G_rsfec
  • 4x25G_nofec 
$more_curr variable supports all target modes.
Note: $mode_curr is not a required parameter.

Example:

In 100GE mode, use this command to switch to 4x25GE: 
run_test_dr_sw $elb "100g_rsfec" "4x25G_nofec"

In 25GE mode, use this command to switch to 4x25GE: 

run_test_dr_sw 0 "" "4x25G_nofec" as
Note: $mode_curr is not required.
dr_calib_switch $elb $mode_curr $mode_target

Reconfigures to a different mode based on the configuration and a $mode_target variable. Performs the PMA adaptation for the specific mode.

$mode_target options:
  • 100G_rsfec
  • 100G_nofec
  • 100G_kpfec6
  • 100G_rsfec_5446
  • 4x25G_rsfec
  • 4x25G_nofec
$more_curr variable supports all target modes.
Note: $mode_curr is not a required parameter.
Example:
  • In 100GE mode, use this command to switch to 4x25GE: dr_calib_switch 0 "100G_rsfec" "4x25G_nofec"
  • In 25GE mode, use this command to switch to 4x25GE: dr_calib_switch 0 "" "4x25G_nofec" as $mode_curr isn't required.
dr_reset Resets all signals except the PMA and E-tile Hard IP for Ethernet CSRs.

Below tables describe dr_reset sequence. You need to assert the 4-bit register in a step pattern: 0x8 > 0xC > 0xE > 0xF > 0xE > 0xC > 0x8 > 0x0. Assume 1 ms delay between each step.

Table 45.  Reset sequence assertionThis table illustrates dr_reset[3:0] assertion sequence.
Assertion Sequence dr_reset[3:0]={Channel3, Channe2, Channe1, Channel0}

Channel 3

Channel 2

Channel 1

Channel 0

(Master Channel)
1 1 0 0 0
2 1 1 0 0
3 1 1 1 0
4 1 1 1 1
Table 46.  Reset sequence deassertionThis table illustrates dr_reset[3:0] deassertion sequence.
Assertion Sequence dr_reset[3:0]={Channel3, Channe2, Channe1, Channel0}

Channel 3

Channel 2

Channel 1

Channel 0

(Master Channel)
1 1 1 1 1
2 1 1 1 0
3 1 1 0 0
4 0 0 0 0
6
Note: These modes are introduced starting from Quartus® Prime Pro Edition software version 22.3.
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