Visible to Intel only — GUID: afc1551418124368
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Visible to Intel only — GUID: afc1551418124368
Ixiasoft
4.1.1. Directory Structure
The E-Tile Dynamic Reconfiguration Design Example file directories contain the following generated files for the design examples.
File Names |
Description |
---|---|
Key Testbench and Simulation Files |
|
<design_example_dir>/example_testbench/basic_avl_tb_top.sv | Top-level testbench file. The testbench instantiates the DUT and runs Verilog HDL tasks to generate and accept packets. |
Testbench Scripts |
|
<design_example_dir>/example_testbench/mentor/run_vsim.do | The Siemens* EDA ModelSim* SE or QuestaSim* script to run the testbench. |
<design_example_dir>/example_testbench/synopsys/run_vcs.sh |
The Synopsys* VCS* script to run the testbench. |
<design_example_dir>/example_testbench/synopsys/run_vcsmx.sh | The Synopsys* VCS* MX script (combined Verilog HDL and SystemVerilog with VHDL) to run the testbench. |
<design_example_dir>/example_testbench/run_xcelium.sh | The Cadence* Xcelium* script to run the testbench. |
File Names |
Description |
---|---|
<design_example_dir>/hardware_test_design/alt_ehipc3.qpf | Quartus® Prime project file |
<design_example_dir>/hardware_test_design/alt_ehipc3.qsf | Quartus® Prime project settings file |
<design_example_dir>/hardware_test_design/alt_ehipc3.sdc | Synopsys Design Constraints files. You can copy and modify these files for your own Intel Agilex® 7 design. |
<design_example_dir>/hardware_test_design/alt_ehipc3.sv | Top-level Verilog HDL design example file |
<design_example_dir>/hardware_test_design/common/ | Hardware design example support files |
File Names |
Description |
---|---|
<design_example_dir>/hardware_test_design/alt_ehipc3_hw.qpf | Quartus® Prime project file |
<design_example_dir>/hardware_test_design/alt_ehipc3_hw.qsf | Quartus® Prime project settings file |
<design_example_dir>/hardware_test_design/alt_ehipc3_hw.sdc | Synopsys Design Constraints files. You can copy and modify these files for your own Intel Agilex® 7 design. |
<design_example_dir>/hardware_test_design/alt_ehipc3_hw.v | Top-level Verilog HDL design example file |
<design_example_dir>/hardware_test_design/common/ | Hardware design example support files |