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2.1.1. Directory Structure
2.1.2. Generating the Design
2.1.3. Simulating the E-tile Ethernet IP for Intel Agilex® 7 FPGA Design Example Testbench
2.1.4. Compiling the Compilation-Only Project
2.1.5. Compiling and Configuring the Design Example in Hardware
2.1.6. Testing the E-tile Ethernet IP for Intel Agilex® 7 FPGA Hardware Design Example
2.2.1.1. Non-PTP 10GE/25GE MAC+PCS with Optional RS-FEC Simulation Design Example
2.2.1.2. PTP 10GE/25GE MAC+PCS with Optional RS-FEC Simulation Design Example
2.2.1.3. 10GE/25GE PCS Only, OTN, or FlexE with Optional RS-FEC Simulation Design Example
2.2.1.4. 10GE/25GE Custom PCS with Optional RS-FEC Simulation Design Example
2.3.1. Simulation Design Examples
2.3.2. Hardware Design Examples
2.3.3. 100GE MAC+PCS with Optional RS-FEC Design Example Interface Signals
2.3.4. 100GE PCS with Optional RS-FEC Design Example Interface Signals
2.3.5. 100GE MAC+PCS with Optional RS-FEC Design Example Registers
2.3.6. 100GE PCS with Optional RS-FEC Design Example Registers
2.3.1.1. Non-PTP E-tile Ethernet IP for Intel Agilex® 7 FPGA 100GE MAC+PCS with Optional RS-FEC Simulation Design Example
2.3.1.2. E-tile Ethernet IP for Intel Agilex® 7 FPGA 100GE MAC+PCS with Optional RS-FEC and PTP Simulation Design Example
2.3.1.3. E-tile Ethernet IP for Intel Agilex® 7 FPGA 100GE PCS Only with Optional RS-FEC Simulation Design Example
2.3.1.4. E-tile Ethernet IP for Intel Agilex® 7 FPGA 100GE OTN with Optional RS-FEC Simulation Design Example
2.3.1.5. E-tile Ethernet IP for Intel Agilex® 7 FPGA 100GE FlexE with Optional RS-FEC Simulation Design Example
2.3.2.1. 100GE MAC+PCS with Optional RS-FEC and PMA Adaptation Flow Hardware Design Example Components
2.3.2.2. 100GE MAC+PCS with Optional RS-FEC and PTP Hardware Design Example
2.3.2.3. 100GE PCS with Optional RS-FEC Hardware Design Example Components
2.3.2.4. Ethernet Adaptation Flow for 100G (CAUI-2) PAM4 <---> 100G (CAUI-4) NRZ Dynamic Reconfiguration Design Example
3.1.1. Hardware and Software Requirements
3.1.2. Generating the Design
3.1.3. Directory Structure
3.1.4. Simulating the Design Example Testbench
3.1.5. Compiling the Compilation-Only Project
3.1.6. Compiling and Configuring the Design Example in Hardware
3.1.7. Testing the E-tile CPRI PHY Intel® FPGA IP Hardware Design Example
4.1. Quick Start Guide
4.2. 10G/25G Ethernet Dynamic Reconfiguration Design Examples
4.3. 25G Ethernet to CPRI Dynamic Reconfiguration Design Example
4.4. CPRI Dynamic Reconfiguration Design Examples
4.5. 100G Ethernet Dynamic Reconfiguration Design Example
4.6. Document Revision History for the E-Tile Dynamic Reconfiguration Design Example
4.5.1. Functional Description
4.5.2. Testing the 100G Ethernet Dynamic Reconfiguration Hardware Design Example
4.5.3. Simulation Design Examples
4.5.4. 100GE DR Hardware Design Examples
4.5.5. 100G Ethernet Dynamic Reconfiguration Design Example Interface Signals
4.5.6. 100G Ethernet Dynamic Reconfiguration Examples Registers
4.5.7. Steps to Enable FEC
4.5.8. Steps to Disable FEC
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2.2.2.1. 10GE/25GE MAC+PCS with Optional RS-FEC and PTP Hardware Design Example Components
Figure 10. 10GE/25GE MAC+PCS with Optional RS-FEC and PTP Hardware Design Example High Level Block Diagram
The E-tile Ethernet IP for Intel Agilex® 7 FPGA hardware design example includes the following components:
- E-tile Ethernet IP for Intel Agilex® 7 FPGA core.
- Client logic that coordinates the programming of the IP core and packet generation.
- Time-of-day (ToD) module to provide a continuous flow of current time-of-day information to the IP core.
- PIO block to store RX and TX PTP timestamp for accuracy calculation and to send PTP 2-step timestamp request.
- Avalon® memory-mapped interface address decoder to decode reconfiguration address space for MAC, transceiver, and RS-FEC modules during reconfiguration accesses.
- JTAG controller that communicates with the System Console. You communicate with the client logic through the System Console.
The following sample output illustrates a successful hardware test run for a 25GE, MAC+PCS, non-PTP IP core variation. The test results are located at <design_example_dir>/hardware_test_design/hwtest_sl/c3_elane_xcvr_loopback_test.log or <design_example_dir>/hardware_test_design/hwtest_sl/c3_elane_traffic_basic_test.log.
Result from c3_elane_xcvr_loopback_test.log file:
Info: Set JTAG Master Service Path Info: Opened JTAG Master Service Test Start time is: 13:08:58 Test Start date is: 03/12/2019 Successfully Write XCVR Channel 0, CSR Register offset = 0x84, data = 0x0 Successfully Write XCVR Channel 0, CSR Register offset = 0x85, data = 0x0 . . . Successfully Read XCVR Channel 0, CSR Register offset = 0x89, data = 0x0 Info: ELANE Channel 0 Internal Loopback initialAdaptation Status Successfully Write XCVR Channel 0, CSR Register offset = 0x84, data = 0x0 Successfully Write XCVR Channel 0, CSR Register offset = 0x85, data = 0xb . . . Successfully Read XCVR Channel 0, CSR Register offset = 0x89, data = 0x0 Info: initialAdaptation is done successfully on channel 0 Successfully Write XCVR Channel 0, CSR Register offset = 0x84, data = 0x0 Successfully Write XCVR Channel 0, CSR Register offset = 0x85, data = 0x8f . . . Successfully Read XCVR Channel 0, CSR Register offset = 0x89, data = 0x0 Successfully Write EHIPLANE Channel 0, User Register phy_ehip_csr_soft_reset , offset = 0x310, data = 0x0 Successfully Write EHIPLANE Channel 0, User Register phy_ehip_csr_soft_reset , offset = 0x310, data = 0x1 . . . Successfully Read EHIPLANE Channel 0, User Register phy_ehip_csr_soft_reset , offset = 0x310, data = 0x0 C3 ELANE Channel 0 System Reset is successfully Test End time is: 13:09:02 Test End date is: 03/12/2019 Info: Closed JTAG Master Service Info: Test <c3_elane_xcvr_loopback_test> Passed
Result from c3_elane_traffic_basic_test.log file:
Info: Set JTAG Master Service Path Info: Opened JTAG Master Service Test Start time is: 13:09:02 Test Start date is: 03/12/2019 Info: Read all ELANE CSR registers Successfully Read EHIPLANE Channel 0, User Register phy_revid , offset = 0x300, data = 0x11112015 Successfully Read EHIPLANE Channel 0, User Register phy_scratch , offset = 0x301, data = 0x0 . . . Successfully Read EHIPLANE Channel 0, User Register phy_ehip_csr_soft_reset , offset = 0x310, data = 0x0 C3 ELANE Channel 0 System Reset is successfully Successfully Write EHIPLANE Channel 0, Traffic GEN/CHK Register pkt_end_addr_start_addr , offset = 0x8, data = 0x25800040 Successfully Write EHIPLANE Channel 0, Traffic GEN/CHK Register pkt_tx_num , offset = 0x9, data = 0xa Info: Stopping the traffic generator Successfully Write EHIPLANE Channel 0, Traffic GEN/CHK Register pkt_tx_ctrl , offset = 0x10, data = 0x87 Info: clearing the traffic generator statistics Successfully Write EHIPLANE Channel 0, Traffic GEN/CHK Register pkt_clear_dropped_counter , offset = 0x7, data = 0x3 Successfully Write EHIPLANE Channel 0, Traffic GEN/CHK Register pkt_clear_dropped_counter , offset = 0x7, data = 0x0 Info: clearing the statistics Successfully Write EHIPLANE Channel 0, User Register cntr_tx_config , offset = 0x845, data = 0x1 Successfully Write EHIPLANE Channel 0, User Register cntr_rx_config , offset = 0x945, data = 0x1 Info: Enabling the statistics Successfully Write EHIPLANE Channel 0, User Register cntr_tx_config , offset = 0x845, data = 0x0 Successfully Write EHIPLANE Channel 0, User Register cntr_rx_config , offset = 0x945, data = 0x0 Info: Starting the traffic generator Successfully Write EHIPLANE Channel 0, Traffic GEN/CHK Register pkt_tx_ctrl , offset = 0x10, data = 0x85 Successfully Read EHIPLANE Channel 0, User Register cntr_tx_fragments_lo , offset = 0x800, data = 0x0 Info: Stopping the traffic generator Successfully Write EHIPLANE Channel 0, Traffic GEN/CHK Register pkt_tx_ctrl , offset = 0x10, data = 0x87 Successfully Read EHIPLANE Channel 0, Traffic GEN/CHK Register pkt_tx_ctrl , offset = 0x10, data = 0x87 . . . Successfully Read EHIPLANE Channel 0, Traffic GEN/CHK Register pkt_rx_pkt_cnt , offset = 0x5, data = 0x463f3f Info: Channel 0 test is completed Successfully Read RSFEC Register rsfec_top_rx_cfg , offset = 0x14, data = 0x1 Successfully Read RSFEC Register arbiter_base_cfg , offset = 0x0, data = 0x1 . . . Successfully Read RSFEC Register rsfec_top_tx_cfg , offset = 0x10, data = 0x6661 Test End time is: 13:09:13 Test End date is: 03/12/2019 Info: Closed JTAG Master Service Info: Test <c3_elane_traffic_basic_test> Passed
The following sample output illustrate a successful hardware test run for a 25GE, MAC+PCS, with PTP IP core variation. The test result is located at <design_example_dir>/hardware_test_design/hwtest_sl/c3_elane_ptp_traffic_basic_test.log.
Info: Set JTAG Master Service Path Info: Opened JTAG Master Service Test Start time is: 17:50:05 Test Start date is: 03/12/2019 Successfully Write EHIPLANE Channel 0, User Register phy_ehip_csr_soft_reset , offset = 0x310, data = 0x0 Successfully Write EHIPLANE Channel 0, User Register phy_ehip_csr_soft_reset , offset = 0x310, data = 0x1 . . . Successfully Read EHIPLANE Channel 0, User Register phy_ehip_csr_soft_reset , offset = 0x310, data = 0x0 C3 ELANE Channel 0 System Reset is successfully Info: Stopping the traffic generator Successfully Write EHIPLANE Channel 0, Traffic GEN/CHK Register pkt_tx_ctrl , offset = 0x10, data = 0x57 Info: clearing the traffic generator statistics Successfully Write EHIPLANE Channel 0, Traffic GEN/CHK Register pkt_clear_dropped_counter , offset = 0x7, data = 0x3 Successfully Write EHIPLANE Channel 0, Traffic GEN/CHK Register pkt_clear_dropped_counter , offset = 0x7, data = 0x0 Info: clearing the statistics Successfully Write EHIPLANE Channel 0, User Register cntr_tx_config , offset = 0x845, data = 0x1 Successfully Write EHIPLANE Channel 0, User Register cntr_rx_config , offset = 0x945, data = 0x1 Info: Enabling the statistics Successfully Write EHIPLANE Channel 0, User Register cntr_tx_config , offset = 0x845, data = 0x0 Successfully Write EHIPLANE Channel 0, User Register cntr_rx_config , offset = 0x945, data = 0x0 . . . Successfully Read EHIPLANE Channel 0, User Register phy_ehip_csr_soft_reset , offset = 0x310, data = 0x0 C3 ELANE Channel 0 System Reset is successfully Info: Training PTP RX AIB deskew and waiting for PTP RX ready... Successfully Read EHIPLANE Channel 0, PIO Register, offset = 0x0, data = 0x5 . . . Successfully Read EHIPLANE Channel 0, PIO Register, offset = 0x0, data = 0x7 Info: PTP RX AIB Deskew Done Info: clearing the traffic generator statistics Successfully Write EHIPLANE Channel 0, Traffic GEN/CHK Register pkt_clear_dropped_counter , offset = 0x7, data = 0x3 Successfully Write EHIPLANE Channel 0, Traffic GEN/CHK Register pkt_clear_dropped_counter , offset = 0x7, data = 0x0 Info: clearing the statistics Successfully Write EHIPLANE Channel 0, User Register cntr_tx_config , offset = 0x845, data = 0x1 Successfully Write EHIPLANE Channel 0, User Register cntr_rx_config , offset = 0x945, data = 0x1 Info: Enabling the statistics Successfully Write EHIPLANE Channel 0, User Register cntr_tx_config , offset = 0x845, data = 0x0 Successfully Write EHIPLANE Channel 0, User Register cntr_rx_config , offset = 0x945, data = 0x0 Info: Accuracy measurement settings Successfully Read RSFEC Register rsfec_cw_pos_rx_3 , offset = 0x1cc, data = 0x2e Info: RX slip count = 0xe Info: UI Value = 0x0009EE01 Info: TX Extra Latency = 0x2c10247 Info: RX Extra Latency = 0x5d17496 Successfully Write EHIPLANE Channel 0, User Register tx_ptp_extra_latency , offset = 0xa0a, data = 0x2c102 . . . Successfully Read EHIPLANE Channel 0, PIO Register, offset = 0xc, data = 0x101 Info: Iteration = 1 : TX Timestamp = 000000000011274d263fa436, RX Timestamp = 000000000011274d263d4680, Accuracy Difference = 2.36605835 ns Successfully Write EHIPLANE Channel 0, PIO Register, offset = 0xc, data = 0x0 Successfully Write EHIPLANE Channel 0, Traffic GEN/CHK Register pkt_tx_ctrl , offset = 0x10, data = 0x57 Successfully Write EHIPLANE Channel 0, PIO Register, offset = 0xc, data = 0x102 Successfully Write EHIPLANE Channel 0, Traffic GEN/CHK Register pkt_tx_ctrl , offset = 0x10, data = 0x55 Successfully Read EHIPLANE Channel 0, User Register cntr_tx_64b_lo , offset = 0x816, data = 0x2 Successfully Read EHIPLANE Channel 0, User Register cntr_rx_64b_lo , offset = 0x916, data = 0x2 Successfully Read EHIPLANE Channel 0, PIO Register, offset = 0x4, data = 0x17137aad Successfully Read EHIPLANE Channel 0, PIO Register, offset = 0x5, data = 0x11284d Successfully Read EHIPLANE Channel 0, PIO Register, offset = 0x6, data = 0x0 Successfully Read EHIPLANE Channel 0, PIO Register, offset = 0x8, data = 0x17111cf7 Successfully Read EHIPLANE Channel 0, PIO Register, offset = 0x9, data = 0x11284d Successfully Read EHIPLANE Channel 0, PIO Register, offset = 0xa, data = 0x0 Successfully Read EHIPLANE Channel 0, PIO Register, offset = 0x7, data = 0x2 Successfully Read EHIPLANE Channel 0, PIO Register, offset = 0xc, data = 0x102 . . . Info: Iteration = 1000 : TX Timestamp = 00000000003331b311e971d6, RX Timestamp = 00000000003331b311e9df10, Accuracy Difference = -0.42666626 ns Info: Stopping the traffic generator Successfully Write EHIPLANE Channel 0, PIO Register, offset = 0xc, data = 0x0 Successfully Write EHIPLANE Channel 0, Traffic GEN/CHK Register pkt_tx_ctrl , offset = 0x10, data = 0x57 . . Successfully Read EHIPLANE Channel 0, User Register cntr_rx_badlt_hi , offset = 0x969, data = 0x0 Test End time is: 17:50:40 Test End date is: 03/12/2019 Info: Closed JTAG Master Service Info: Test <c3_elane_ptp_traffic_basic_test> Passed