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2.1.1. Directory Structure
2.1.2. Generating the Design
2.1.3. Simulating the E-tile Ethernet IP for Intel Agilex® 7 FPGA Design Example Testbench
2.1.4. Compiling the Compilation-Only Project
2.1.5. Compiling and Configuring the Design Example in Hardware
2.1.6. Testing the E-tile Ethernet IP for Intel Agilex® 7 FPGA Hardware Design Example
2.2.1.1. Non-PTP 10GE/25GE MAC+PCS with Optional RS-FEC Simulation Design Example
2.2.1.2. PTP 10GE/25GE MAC+PCS with Optional RS-FEC Simulation Design Example
2.2.1.3. 10GE/25GE PCS Only, OTN, or FlexE with Optional RS-FEC Simulation Design Example
2.2.1.4. 10GE/25GE Custom PCS with Optional RS-FEC Simulation Design Example
2.3.1. Simulation Design Examples
2.3.2. Hardware Design Examples
2.3.3. 100GE MAC+PCS with Optional RS-FEC Design Example Interface Signals
2.3.4. 100GE PCS with Optional RS-FEC Design Example Interface Signals
2.3.5. 100GE MAC+PCS with Optional RS-FEC Design Example Registers
2.3.6. 100GE PCS with Optional RS-FEC Design Example Registers
2.3.1.1. Non-PTP E-tile Ethernet IP for Intel Agilex® 7 FPGA 100GE MAC+PCS with Optional RS-FEC Simulation Design Example
2.3.1.2. E-tile Ethernet IP for Intel Agilex® 7 FPGA 100GE MAC+PCS with Optional RS-FEC and PTP Simulation Design Example
2.3.1.3. E-tile Ethernet IP for Intel Agilex® 7 FPGA 100GE PCS Only with Optional RS-FEC Simulation Design Example
2.3.1.4. E-tile Ethernet IP for Intel Agilex® 7 FPGA 100GE OTN with Optional RS-FEC Simulation Design Example
2.3.1.5. E-tile Ethernet IP for Intel Agilex® 7 FPGA 100GE FlexE with Optional RS-FEC Simulation Design Example
2.3.2.1. 100GE MAC+PCS with Optional RS-FEC and PMA Adaptation Flow Hardware Design Example Components
2.3.2.2. 100GE MAC+PCS with Optional RS-FEC and PTP Hardware Design Example
2.3.2.3. 100GE PCS with Optional RS-FEC Hardware Design Example Components
2.3.2.4. Ethernet Adaptation Flow for 100G (CAUI-2) PAM4 <---> 100G (CAUI-4) NRZ Dynamic Reconfiguration Design Example
3.1.1. Hardware and Software Requirements
3.1.2. Generating the Design
3.1.3. Directory Structure
3.1.4. Simulating the Design Example Testbench
3.1.5. Compiling the Compilation-Only Project
3.1.6. Compiling and Configuring the Design Example in Hardware
3.1.7. Testing the E-tile CPRI PHY Intel® FPGA IP Hardware Design Example
4.1. Quick Start Guide
4.2. 10G/25G Ethernet Dynamic Reconfiguration Design Examples
4.3. 25G Ethernet to CPRI Dynamic Reconfiguration Design Example
4.4. CPRI Dynamic Reconfiguration Design Examples
4.5. 100G Ethernet Dynamic Reconfiguration Design Example
4.6. Document Revision History for the E-Tile Dynamic Reconfiguration Design Example
4.5.1. Functional Description
4.5.2. Testing the 100G Ethernet Dynamic Reconfiguration Hardware Design Example
4.5.3. Simulation Design Examples
4.5.4. 100GE DR Hardware Design Examples
4.5.5. 100G Ethernet Dynamic Reconfiguration Design Example Interface Signals
4.5.6. 100G Ethernet Dynamic Reconfiguration Examples Registers
4.5.7. Steps to Enable FEC
4.5.8. Steps to Disable FEC
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2.2.1.4. 10GE/25GE Custom PCS with Optional RS-FEC Simulation Design Example
The simulation block diagram below is generated using the following settings in the IP parameter editor:
- Under the IP tab:
- Custom PCS with optional RSFEC as the core variant.
- Enable RSFEC to use the RS-FEC feature.
- Under the Custom PCS Channel(s) tab:
- PCS+RSFEC as the custom PCS mode.
Figure 9. Simulation Block Diagram for E-tile Ethernet IP for Intel Agilex® 7 FPGA 10GE/25GE Custom PCS with Optional RS-FEC Design Example
The testbench sends traffic through the IP core, exercising the transmit side and receive side of the IP core.
The successful test run displays output confirming the following behavior:
- Wait for PLL to lock.
- Wait for RX transceiver reset to complete.
- Wait for RX alignment.
- Send three sets of packet.
- Receive and verify the packets.
- Displaying Testbench complete.
The following sample output illustrates a successful simulation test run for a 10GE, custom PCS, RS-FEC IP core variation.
Ref clock is 184.320000 MHz Channel 0 - waiting for EHIP Ready.... Channel 0 - EHIP READY is 1 at time 382745000 Channel 0 - Waiting for RX Block Lock Channel 0 - EHIP RX Block Lock is high at time 387137583 Channel 0 - Waiting for RX alignment Channel 0 - RX deskew locked Channel 0 - RX lane aligmnent locked Channel 0 - TX enabled *** Channel 0 - Sending packets *** Start frame detected, byteslip 0, time 389768227 ** Channel 0 - RX checker has received packets correctly! ** Channel 0 - RX checker is reset. *** Channel 0 - Second attempt of sending packets *** Start frame detected, byteslip 0, time 395241712 ** Channel 0 - RX checker has received packets correctly! ** Channel 0 - RX checker is reset. *** Channel 0 - Third attempt of sending packets *** Start frame detected, byteslip 0, time 400721512 ** Channel 0 - RX checker has received packets correctly! Channel 1 - waiting for EHIP Ready.... Channel 1 - EHIP READY is 1 at time 403524543 Channel 1 - Waiting for RX Block Lock Channel 1 - EHIP RX Block Lock is high at time 403524543 Channel 1 - Waiting for RX alignment Channel 1 - RX deskew locked Channel 1 - RX lane aligmnent locked Channel 1 - TX enabled *** Channel 1 - Sending packets *** Start frame detected, byteslip 0, time 406113519 ** Channel 1 - RX checker has received packets correctly! ** Channel 1 - RX checker is reset. *** Channel 1 - Second attempt of sending packets *** Start frame detected, byteslip 0, time 411605943 ** Channel 1 - RX checker has received packets correctly! ** Channel 1 - RX checker is reset. *** Channel 1 - Third attempt of sending packets *** Start frame detected, byteslip 0, time 417092055 ** Channel 1 - RX checker has received packets correctly! Channel 2 - waiting for EHIP Ready.... Channel 2 - EHIP READY is 1 at time 419907712 Channel 2 - Waiting for RX Block Lock Channel 2 - EHIP RX Block Lock is high at time 419907712 Channel 2 - Waiting for RX alignment Channel 2 - RX deskew locked Channel 2 - RX lane aligmnent locked Channel 2 - TX enabled *** Channel 2 - Sending packets *** Start frame detected, byteslip 0, time 422502903 ** Channel 2 - RX checker has received packets correctly! ** Channel 2 - RX checker is reset. *** Channel 2 - Second attempt of sending packets *** Start frame detected, byteslip 0, time 428007954 ** Channel 2 - RX checker has received packets correctly! ** Channel 2 - RX checker is reset. *** Channel 2 - Third attempt of sending packets *** Start frame detected, byteslip 0, time 433494066 ** Channel 2 - RX checker has received packets correctly! Channel 3 - waiting for EHIP Ready.... Channel 3 - EHIP READY is 1 at time 436322349 Channel 3 - Waiting for RX Block Lock Channel 3 - EHIP RX Block Lock is high at time 436322349 Channel 3 - Waiting for RX alignment Channel 3 - RX deskew locked Channel 3 - RX lane aligmnent locked Channel 3 - TX enabled *** Channel 3 - Sending packets *** Start frame detected, byteslip 0, time 438905013 ** Channel 3 - RX checker has received packets correctly! ** Channel 3 - RX checker is reset. *** Channel 3 - Second attempt of sending packets *** Start frame detected, byteslip 0, time 444384812 ** Channel 3 - RX checker has received packets correctly! ** Channel 3 - RX checker is reset. *** Channel 3 - Third attempt of sending packets *** Start frame detected, byteslip 0, time 449864611 ** Channel 3 - RX checker has received packets correctly! ** PASSED ** ***************************************** $finish called from file "basic_avl_tb_top.sv", line 285. $finish at simulation time 452773953718