E-Tile Hard IP Agilex™ 7 Design Example User Guide: Ethernet, E-tile CPRI PHY and Dynamic Reconfiguration

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ID 683860
Date 4/30/2024
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Document Table of Contents
Document Table of Contents x
1. About E-tile Hard IP Agilex™ 7 Design Example User Guide 2. E-Tile Ethernet IP for Agilex™ 7 FPGA Design Example 3. E-tile CPRI PHY Intel® FPGA IP Design Example 4. E-Tile Dynamic Reconfiguration Design Example 5. E-tile Hard IP Agilex™ 7 Design Examples User Guide Archives
2. E-Tile Ethernet IP for Agilex™ 7 FPGA Design Example x
2.1. Quick Start Guide 2.2. 10GE/25GE with Optional RS-FEC Design Examples 2.3. 100GE with Optional RS-FEC Design Example 2.4. Ethernet Toolkit Overview 2.5. Document Revision History for the E-tile Hard IP for Ethernet Agilex™ 7 FPGA IP Design Example User Guide
2.1. Quick Start Guide x
2.1.1. Directory Structure 2.1.2. Generating the Design 2.1.3. Simulating the E-tile Ethernet IP for Intel Agilex® 7 FPGA Design Example Testbench 2.1.4. Compiling the Compilation-Only Project 2.1.5. Compiling and Configuring the Design Example in Hardware 2.1.6. Testing the E-tile Ethernet IP for Intel Agilex® 7 FPGA Hardware Design Example
2.1.3. Simulating the E-tile Ethernet IP for Intel Agilex® 7 FPGA Design Example Testbench x
2.1.3.1. Fast Sim Model for E-tile Ethernet IP for Intel Agilex® 7 FPGA
2.1.6. Testing the E-tile Ethernet IP for Intel Agilex® 7 FPGA Hardware Design Example x
2.1.6.1. 10GE/25GE Design Example 2.1.6.2. 100GE MAC+PCS with Optional (528,514) RS-FEC or (544,514) RS-FEC and Adaptation Flow Hardware Design Example 2.1.6.3. 100GE PCS Only with Optional (528,514) RS-FEC or (544,514) RS-FEC, and Optional PTP Hardware Design Example
2.2. 10GE/25GE with Optional RS-FEC Design Examples x
2.2.1. Simulation Design Examples 2.2.2. Hardware Design Examples 2.2.3. 10GE/25GE Design Example Interface Signals 2.2.4. 10GE/25GE Design Examples Registers
2.2.1. Simulation Design Examples x
2.2.1.1. Non-PTP 10GE/25GE MAC+PCS with Optional RS-FEC Simulation Design Example 2.2.1.2. PTP 10GE/25GE MAC+PCS with Optional RS-FEC Simulation Design Example 2.2.1.3. 10GE/25GE PCS Only, OTN, or FlexE with Optional RS-FEC Simulation Design Example 2.2.1.4. 10GE/25GE Custom PCS with Optional RS-FEC Simulation Design Example
2.2.2. Hardware Design Examples x
2.2.2.1. 10GE/25GE MAC+PCS with Optional RS-FEC and PTP Hardware Design Example Components 2.2.2.2. 10GE/25GE PCS Only with Optional RS-FEC Hardware Design Example Components 2.2.2.3. 10GE/25GE Custom PCS with Optional RS-FEC Hardware Design Example
2.3. 100GE with Optional RS-FEC Design Example x
2.3.1. Simulation Design Examples 2.3.2. Hardware Design Examples 2.3.3. 100GE MAC+PCS with Optional RS-FEC Design Example Interface Signals 2.3.4. 100GE PCS with Optional RS-FEC Design Example Interface Signals 2.3.5. 100GE MAC+PCS with Optional RS-FEC Design Example Registers 2.3.6. 100GE PCS with Optional RS-FEC Design Example Registers
2.3.1. Simulation Design Examples x
2.3.1.1. Non-PTP E-tile Ethernet IP for Intel Agilex® 7 FPGA 100GE MAC+PCS with Optional RS-FEC Simulation Design Example 2.3.1.2. E-tile Ethernet IP for Intel Agilex® 7 FPGA 100GE MAC+PCS with Optional RS-FEC and PTP Simulation Design Example 2.3.1.3. E-tile Ethernet IP for Intel Agilex® 7 FPGA 100GE PCS Only with Optional RS-FEC Simulation Design Example 2.3.1.4. E-tile Ethernet IP for Intel Agilex® 7 FPGA 100GE OTN with Optional RS-FEC Simulation Design Example 2.3.1.5. E-tile Ethernet IP for Intel Agilex® 7 FPGA 100GE FlexE with Optional RS-FEC Simulation Design Example
2.3.2. Hardware Design Examples x
2.3.2.1. 100GE MAC+PCS with Optional RS-FEC and PMA Adaptation Flow Hardware Design Example Components 2.3.2.2. 100GE MAC+PCS with Optional RS-FEC and PTP Hardware Design Example 2.3.2.3. 100GE PCS with Optional RS-FEC Hardware Design Example Components 2.3.2.4. Ethernet Adaptation Flow for 100G (CAUI-2) PAM4 <---> 100G (CAUI-4) NRZ Dynamic Reconfiguration Design Example
2.4. Ethernet Toolkit Overview x
2.4.1. Features
3. E-tile CPRI PHY Intel® FPGA IP Design Example x
3.1. E-tile CPRI PHY Intel® FPGA IP Quick Start Guide 3.2. E-tile CPRI PHY Design Example Description 3.3. Document Revision History for the E-tile CPRI PHY Intel® FPGA IP Design Example User Guide
3.1. E-tile CPRI PHY Intel® FPGA IP Quick Start Guide x
3.1.1. Hardware and Software Requirements 3.1.2. Generating the Design 3.1.3. Directory Structure 3.1.4. Simulating the Design Example Testbench 3.1.5. Compiling the Compilation-Only Project 3.1.6. Compiling and Configuring the Design Example in Hardware 3.1.7. Testing the E-tile CPRI PHY Intel® FPGA IP Hardware Design Example
3.2. E-tile CPRI PHY Design Example Description x
3.2.1. Features 3.2.2. Simulation Design Example 3.2.3. Hardware Design Example 3.2.4. Interface Signals 3.2.5. Design Example Register Map for Reconfiguration
4. E-Tile Dynamic Reconfiguration Design Example x
4.1. Quick Start Guide 4.2. 10G/25G Ethernet Dynamic Reconfiguration Design Examples 4.3. 25G Ethernet to CPRI Dynamic Reconfiguration Design Example 4.4. CPRI Dynamic Reconfiguration Design Examples 4.5. 100G Ethernet Dynamic Reconfiguration Design Example 4.6. Document Revision History for the E-Tile Dynamic Reconfiguration Design Example
4.1. Quick Start Guide x
4.1.1. Directory Structure 4.1.2. Generating the Design 4.1.3. Simulating the E-Tile Dynamic Reconfiguration Design Example Testbench 4.1.4. Compiling and Configuring the Design Example in Hardware 4.1.5. Testing the E-Tile Dynamic Reconfiguration Hardware Design Example
4.1.2. Generating the Design x
4.1.2.1. Design Example Parameters
4.1.3. Simulating the E-Tile Dynamic Reconfiguration Design Example Testbench x
4.1.3.1. Running the Simulation 4.1.3.2. Generating New HEX File Using Eclipse-based Ashling RiscFree IDE Tool 4.1.3.3. Performing the Link Initialization
4.1.5. Testing the E-Tile Dynamic Reconfiguration Hardware Design Example x
4.1.5.1. Running the Design Example in Hardware 4.1.5.2. Power Management Setting for Agilex™ 7 Transceiver Signal Integrity Development Kit
4.2. 10G/25G Ethernet Dynamic Reconfiguration Design Examples x
4.2.1. Functional Description 4.2.2. Simulation Design Examples 4.2.3. Hardware Design Examples 4.2.4. 10GE/25GE Design Example Interface Signals 4.2.5. 10GE/25GE Design Examples Registers 4.2.6. Dynamic Reconfiguration Flow for 25GbE PTP FEC to 25GbE PTP Non-FEC
4.2.1. Functional Description x
4.2.1.1. Clocking Scheme
4.2.2. Simulation Design Examples x
4.2.2.1. 10GE/25GE MAC+PCS with RS-FEC and PTP Simulation Dynamic Reconfiguration Design Example Components 4.2.2.2. 10GE/25GE MAC+PCS with RS-FEC Simulation Dynamic Reconfiguration Design Example Components
4.2.3. Hardware Design Examples x
4.2.3.1. 10GE/25GE MAC+PCS with RS-FEC and PTP Hardware Dynamic Reconfiguration Design Example Components 4.2.3.2. 10GE/25GE MAC+PCS with RS-FEC Hardware Dynamic Reconfiguration Design Example Components
4.3. 25G Ethernet to CPRI Dynamic Reconfiguration Design Example x
4.3.1. Functional Description 4.3.2. Simulation Design Examples 4.3.3. Hardware Design Examples 4.3.4. 25G Ethernet to CPRI Design Example Interface Signals 4.3.5. 25G Ethernet to CPRI Design Examples Registers 4.3.6. Dynamic Reconfiguration Flow for 25GbE PTP FEC to 24G CPRI FEC
4.3.1. Functional Description x
4.3.1.1. Clocking Scheme 4.3.1.2. Reset
4.3.2. Simulation Design Examples x
4.3.2.1. 25GE MAC+PCS with RS-FEC and PTP to CPRI Simulation Dynamic Reconfiguration Design Example Components
4.3.3. Hardware Design Examples x
4.3.3.1. 25GE MAC+PCS with RS-FEC and PTP to CPRI Hardware Dynamic Reconfiguration Design Example Components
4.4. CPRI Dynamic Reconfiguration Design Examples x
4.4.1. Functional Description 4.4.2. Simulation Design Examples 4.4.3. Hardware Design Examples 4.4.4. CPRI Design Example Interface Signals 4.4.5. CPRI Design Example Registers 4.4.6. Dynamic Reconfiguration Flow for 24G CPRI FEC to 24G CPRI Non-FEC
4.4.1. Functional Description x
4.4.1.1. Clocking Scheme
4.4.2. Simulation Design Examples x
4.4.2.1. 24G CPRI PHY with RS-FEC Simulation Dynamic Reconfiguration Design Example Components 4.4.2.2. 9.8G CPRI PHY Simulation Dynamic Reconfiguration Design Example Components
4.4.3. Hardware Design Examples x
4.4.3.1. CPRI PHY with RS-FEC Hardware Dynamic Reconfiguration Design Example Components
4.5. 100G Ethernet Dynamic Reconfiguration Design Example x
4.5.1. Functional Description 4.5.2. Testing the 100G Ethernet Dynamic Reconfiguration Hardware Design Example 4.5.3. Simulation Design Examples 4.5.4. 100GE DR Hardware Design Examples 4.5.5. 100G Ethernet Dynamic Reconfiguration Design Example Interface Signals 4.5.6. 100G Ethernet Dynamic Reconfiguration Examples Registers 4.5.7. Steps to Enable FEC 4.5.8. Steps to Disable FEC
4.5.2. Testing the 100G Ethernet Dynamic Reconfiguration Hardware Design Example x
4.5.2.1. Dynamic Reconfiguration Flow in 100G Ethernet Dynamic Reconfiguration Example Design
4.5.3. Simulation Design Examples x
4.5.3.1. 100GE MAC+PCS with Optional RS-FEC Dynamic Reconfiguration Simulation Design Example 4.5.3.2. Simulating the E-tile Ethernet IP for Intel Agilex® 7 FPGA Design Example Testbench
4.5.4. 100GE DR Hardware Design Examples x
4.5.4.1. 100GE MAC+PCS with Optional RS-FEC Dynamic Reconfiguration Hardware Design Example Components
4.5.7. Steps to Enable FEC x
4.5.7.1. Configuring for 100G NRZ with RSFEC [KR-FEC (528,514)] 4.5.7.2. Configuring for 100G NRZ with RSFEC [KP-FEC (544,514)] 4.5.7.3. Configuring for 100G PAM4 with RSFEC [KP-FEC (544,514)]
1. About E-tile Hard IP Agilex™ 7 Design Example User Guide
2. E-Tile Ethernet IP for Agilex™ 7 FPGA Design Example
3. E-tile CPRI PHY Intel® FPGA IP Design Example
4. E-Tile Dynamic Reconfiguration Design Example
5. E-tile Hard IP Agilex™ 7 Design Examples User Guide Archives

2.3.2.2. 100GE MAC+PCS with Optional RS-FEC and PTP Hardware Design Example

Figure 19. 100GE MAC + PCS with Optional RS-FEC and PTP Hardware Design Examples High Level Block Diagram
The E-tile Ethernet IP for Intel Agilex® 7 FPGA hardware design example includes the following components:
  • E-tile Ethernet IP for Intel Agilex® 7 FPGA core.
  • Client logic that coordinates the programming of the IP core and packet generation.
  • Time-of-day (ToD) module to provide a continuous flow of current time-of-day information to the IP core.
  • PIO block to store RX and TX PTP timestamp for accuracy calculation and to send PTP 2-step timestamp request.
  • Avalon® memory-mapped interface address decoder to decode reconfiguration address space for MAC, transceiver, and RS-FEC modules during reconfiguration accesses.
  • JTAG controller that communicates with the System Console. You communicate with the client logic through the System Console.

The following sample output illustrates a successful hardware test run for a 100GE, MAC+PCS with RS-FEC, non-PTP IP core variation. The test results are located at <design_example_dir>/hardware_test_design/hwtest_ptp/c3_elane_xcvr_loopback_test.log or <design_example_dir>/hardware_test_design/hwtest_ptp/c3_elane_traffic_basic_test.log.

Result from c3_elane_xcvr_loopback_test.log file: 
Info: Set JTAG Master Service Path


Info: Opened JTAG Master Service

	Test Start time is: 13:25:08
	Test Start date is: 03/04/2019


Info: Cycling reset ...
	Successfully Write Channel 0 XCVR CSR Register offset = 0x84, data = 0x1 
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	Successfully Read  Channel 0 XCVR CSR Register offset = 0x88, data = 0x8 

	C3 EHIP XCVR Channel 0 Loopback mode is successfully enabled 

	Successfully Write Channel 1 XCVR CSR Register offset = 0x84, data = 0x1 
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	Successfully Read  Channel 1 XCVR CSR Register offset = 0x88, data = 0x8 

	C3 EHIP XCVR Channel 1 Loopback mode is successfully enabled 
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	Successfully Read  Channel 2 XCVR CSR Register offset = 0x88, data = 0x8 

	C3 EHIP XCVR Channel 2 Loopback mode is successfully enabled 

	Successfully Write Channel 3 XCVR CSR Register offset = 0x84, data = 0x1 
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	Successfully Write Channel 3 XCVR CSR Register offset = 0x8a, data = 0x80 
	Successfully Read  Channel 3 XCVR CSR Register offset = 0x88, data = 0x8 

	C3 EHIP XCVR Channel 3 Loopback mode is successfully enabled 

	Successfully Write EHIP User Register phy_ehip_csr_soft_reset               , offset = 0x310, data = 0x0 
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	Successfully Read  EHIP User Register phy_ehip_csr_soft_reset               , offset = 0x310, data = 0x0 

	C3 EHIP System Reset is successfully 

	Test End time is: 13:25:09
	Test End date is: 03/04/2019

Info: Closed JTAG Master Service


Info: Test <c3_ehip_xcvr_loopback_test> Passed
Result from c3_elane_traffic_basic_test_log file: 
Info: Set JTAG Master Service Path


Info: Opened JTAG Master Service

	Test Start time is: 13:25:09
	Test Start date is: 03/04/2019


Info: Read all EHIP CSR registers

	Successfully Read  EHIP User Register phy_revid                              , offset = 0x300, data = 0x11112015 
	Successfully Read  EHIP User Register phy_scratch                           , offset = 0x301, data = 0x0 
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	Successfully Read  EHIP User Register phy_ehip_csr_soft_reset               , offset = 0x310, data = 0x0 

	C3 EHIP System Reset is successfully 


Info: Stopping the traffic generator

	Successfully Write EHIP Traffic GEN/CHK Register, offset = 0x10, data = 0x87 

Info: clearing the statistics

	Successfully Write EHIP User Register cntr_tx_config                        , offset = 0x845, data = 0x1 
	Successfully Write EHIP User Register cntr_rx_config                        , offset = 0x945, data = 0x1 

Info: Enabling the statistics

	Successfully Write EHIP User Register cntr_tx_config                        , offset = 0x845, data = 0x0 
	Successfully Write EHIP User Register cntr_rx_config                        , offset = 0x945, data = 0x0 

Info: Starting the traffic generator

	Successfully Write EHIP Traffic GEN/CHK Register, offset = 0x10, data = 0x85 
	Successfully Read  EHIP User Register cntr_tx_fragments_lo                  , offset = 0x800, data = 0x0 

Info: Stopping the traffic generator

	Successfully Write EHIP Traffic GEN/CHK Register, offset = 0x10, data = 0x87 
	Successfully Read  EHIP Traffic GEN/CHK Register, offset = 0x10, data = 0x87 
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	Successfully Read  EHIP User Register cntr_rx_badlt_hi                      , offset = 0x969, data = 0x0 

Info: Test iteration 1 is completed 

	Successfully Read  RSFEC Register rsfec_top_rx_cfg                     , offset = 0x14, data = 0x1111 
	Successfully Read  RSFEC Register arbiter_base_cfg                      , offset = 0x0, data = 0x1 
	Successfully Read  RSFEC Register rsfec_top_clk_cfg                    , offset = 0x4, data = 0xf00 
	Successfully Read  RSFEC Register rsfec_top_tx_cfg                     , offset = 0x10, data = 0x0 
	Successfully Write RSFEC Register rsfec_top_tx_cfg                     , offset = 0x10, data = 0x10001666 
	Successfully Read  RSFEC Register rsfec_top_tx_cfg                     , offset = 0x10, data = 0x10001666 
	Successfully Write RSFEC Register rsfec_top_tx_cfg                     , offset = 0x10, data = 0x0 
	Successfully Read  RSFEC Register rsfec_top_tx_cfg                     , offset = 0x10, data = 0x0 

	Test End time is: 13:25:21
	Test End date is: 03/04/2019

Info: Closed JTAG Master Service


Info: Test <c3_ehip_traffic_basic_test> Passed
The following sample output illustrates a successful hardware test run for a 100GE, MAC+PCS with RS-FEC, PTP IP core variation. The test result is located at <design_example_dir>/hardware_test_design/hwtest_ptp/c3_elane_ptp_traffic_basic_test.log. 
Info: Set JTAG Master Service Path


Info: Opened JTAG Master Service

	Test Start time is: 13:25:21
	Test Start date is: 03/04/2019

	Successfully Write EHIP User Register phy_ehip_csr_soft_reset               , offset = 0x310, data = 0x0 
	Successfully Write EHIP User Register phy_ehip_csr_soft_reset               , offset = 0x310, data = 0x1 
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	Successfully Read  EHIP User Register phy_ehip_csr_soft_reset               , offset = 0x310, data = 0x0 

	C3 EHIP System Reset is successfully 

	Successfully Write Channel 0 XCVR CSR Register offset = 0x84, data = 0x0 
	Successfully Write Channel 0 XCVR CSR Register offset = 0x85, data = 0x0 
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	Successfully Write Channel 3 XCVR CSR Register offset = 0x93, data = 0x0 
Internal Loopback iCal Status
	Successfully Write Channel 0 XCVR CSR Register offset = 0x84, data = 0x0 
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	Successfully Write Channel 0 XCVR CSR Register offset = 0x93, data = 0x0 
iCal is done successfully on channel 0
	Successfully Write Channel 1 XCVR CSR Register offset = 0x84, data = 0x0 
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. 

	Successfully Write Channel 3 XCVR CSR Register offset = 0x93, data = 0x0 

Info: Cycling reset ...
	Successfully Write EHIP Traffic GEN/CHK Register, offset = 0x8, data = 0x40 
	Successfully Write EHIP Traffic GEN/CHK Register, offset = 0x9, data = 0x1 
	Successfully Read  EHIP Traffic GEN/CHK Register, offset = 0x9, data = 0x1 

Info: clearing the statistics

	Successfully Write EHIP User Register cntr_tx_config                        , offset = 0x845, data = 0x1 
	Successfully Write EHIP User Register cntr_rx_config                        , offset = 0x945, data = 0x1 

Info: Enabling the statistics

	Successfully Write EHIP User Register cntr_tx_config                        , offset = 0x845, data = 0x0 
	Successfully Write EHIP User Register cntr_rx_config                        , offset = 0x945, data = 0x0 

Info: Accuracy measurement settings

Info: UI Value = 0x0009EE01 

Info: TX Extra Latency = 0xc69814 

Info: RX Extra Latency = 0x5467088 

	Successfully Write EHIP User Register tx_ptp_extra_latency                  , offset = 0xa0a, data = 0xc698 
	Successfully Read  EHIP User Register tx_ptp_extra_latency                  , offset = 0xa0a, data = 0xc698 
	Successfully Write EHIP User Register rx_ptp_extra_latency                  , offset = 0xb06, data = 0x80054670 
	Successfully Read  EHIP User Register rx_ptp_extra_latency                  , offset = 0xb06, data = 0x80054670 

Info: Waiting for VL offset data ready

	Successfully Read  EHIP Soft PTP Register vl_offset_data0_lo                    , offset = 0xc10, data = 0xc000008c 

Info: All VL data reading, calculation of VL offset and reloading new VL offset...

Reading FEC lane mapping and deskew ...
Lane map 0 = 0
Lane map 1 = 1
Lane map 2 = 2
Lane map 3 = 3
Lane 0 skew = 1
Lane 1 skew = 2
Lane 2 skew = 1
Lane 3 skew = 2

++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
gen_vl_data_fec: Input Deskew_delay = 0x00000001
gen_vl_data_fec: Input Selected_pl  = 0
++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++

============================================================================================

before-rotation: VL[PL] 0[0], deskew_delay = 0x1 UI, vl_offset_bits = 1
After Rotation: calc_vl_offset done - RVL 4, LPL 0, LVL 0 Sign=0, NS=0, FNS=2542


For LOCAL_VL=0 --> CALC_VL_OFFSET=0x000009EE, LOCAL_PL=0, REMOTE_VL=4
Final Calculated value - 325380

============================================================================================
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============================================================================================

before-rotation: VL[PL] 19[0], deskew_delay = 0x1 UI, vl_offset_bits = 5
before-rotation: VL[PL] 19[0], deskew_delay = 0x1 UI, vl_offset_bits_shifted = -325
After Rotation: calc_vl_offset done - RVL 3, LPL 0, LVL 19 Sign=1, NS=12, FNS=39719


For LOCAL_VL=19 --> CALC_VL_OFFSET=0x800C9B27, LOCAL_PL=0, REMOTE_VL=3
Final Calculated value - 274983654275

============================================================================================


	
Writing new VL offsets ...
write_vl_offset Loading vls data.....
	Successfully Write EHIP Soft PTP Register vl_offset0_lo                         , offset = 0xc40, data = 0x4 
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	Successfully Write EHIP Soft PTP Register vl_offset19_hi                        , offset = 0xc67, data = 0x800c9b27 

Info: Waiting for PTP RX ready...

	Successfully Read  EHIP PIO Register, offset = 0x0, data = 0x7 
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	Successfully Read  EHIP PIO Register, offset = 0xc, data = 0x101 

Info: Iteration = 1 : TX Timestamp = 0000000000060ca82f0f8fa7,  RX Timestamp = 0000000000060ca82f0e78eb,  Accuracy Difference = -1.08880615 ns 

	Successfully Write EHIP PIO Register, offset = 0xc, data = 0x0 
	Successfully Write EHIP Traffic GEN/CHK Register, offset = 0x10, data = 0x57 
	Successfully Write EHIP PIO Register, offset = 0xc, data = 0x102 
	Successfully Write EHIP Traffic GEN/CHK Register, offset = 0x10, data = 0x55 
	Successfully Read  EHIP User Register cntr_tx_64b_lo                        , offset = 0x816, data = 0x2 
	Successfully Read  EHIP User Register cntr_rx_64b_lo                        , offset = 0x916, data = 0x2 
	Successfully Read  EHIP PIO Register, offset = 0x4, data = 0x90e52f43 
	Successfully Read  EHIP PIO Register, offset = 0x5, data = 0x60f25 
	Successfully Read  EHIP PIO Register, offset = 0x6, data = 0x0 
	Successfully Read  EHIP PIO Register, offset = 0x8, data = 0x90e68e57 
	Successfully Read  EHIP PIO Register, offset = 0x9, data = 0x60f25 
	Successfully Read  EHIP PIO Register, offset = 0xa, data = 0x0 
	Successfully Read  EHIP PIO Register, offset = 0x7, data = 0x2 
	Successfully Read  EHIP PIO Register, offset = 0xc, data = 0x102 

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Info: Iteration = 100 : TX Timestamp = 00000000000a1d8d0ad81ed6,  RX Timestamp = 00000000000a1d8d0ad982d9,  Accuracy Difference = 1.39067078 ns 


Info: Stopping the traffic generator

	Successfully Write EHIP PIO Register, offset = 0xc, data = 0x0 
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	Successfully Read  EHIP User Register cntr_rx_badlt_hi                      , offset = 0x969, data = 0x0 

	Test End time is: 13:25:39
	Test End date is: 03/04/2019

Info: Closed JTAG Master Service



Info: Test <c3_ehip_ptp_traffic_basic_test> Passed
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