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2.1.1. Directory Structure
2.1.2. Generating the Design
2.1.3. Simulating the E-tile Ethernet IP for Intel Agilex® 7 FPGA Design Example Testbench
2.1.4. Compiling the Compilation-Only Project
2.1.5. Compiling and Configuring the Design Example in Hardware
2.1.6. Testing the E-tile Ethernet IP for Intel Agilex® 7 FPGA Hardware Design Example
2.2.1.1. Non-PTP 10GE/25GE MAC+PCS with Optional RS-FEC Simulation Design Example
2.2.1.2. PTP 10GE/25GE MAC+PCS with Optional RS-FEC Simulation Design Example
2.2.1.3. 10GE/25GE PCS Only, OTN, or FlexE with Optional RS-FEC Simulation Design Example
2.2.1.4. 10GE/25GE Custom PCS with Optional RS-FEC Simulation Design Example
2.3.1. Simulation Design Examples
2.3.2. Hardware Design Examples
2.3.3. 100GE MAC+PCS with Optional RS-FEC Design Example Interface Signals
2.3.4. 100GE PCS with Optional RS-FEC Design Example Interface Signals
2.3.5. 100GE MAC+PCS with Optional RS-FEC Design Example Registers
2.3.6. 100GE PCS with Optional RS-FEC Design Example Registers
2.3.1.1. Non-PTP E-tile Ethernet IP for Intel Agilex® 7 FPGA 100GE MAC+PCS with Optional RS-FEC Simulation Design Example
2.3.1.2. E-tile Ethernet IP for Intel Agilex® 7 FPGA 100GE MAC+PCS with Optional RS-FEC and PTP Simulation Design Example
2.3.1.3. E-tile Ethernet IP for Intel Agilex® 7 FPGA 100GE PCS Only with Optional RS-FEC Simulation Design Example
2.3.1.4. E-tile Ethernet IP for Intel Agilex® 7 FPGA 100GE OTN with Optional RS-FEC Simulation Design Example
2.3.1.5. E-tile Ethernet IP for Intel Agilex® 7 FPGA 100GE FlexE with Optional RS-FEC Simulation Design Example
2.3.2.1. 100GE MAC+PCS with Optional RS-FEC and PMA Adaptation Flow Hardware Design Example Components
2.3.2.2. 100GE MAC+PCS with Optional RS-FEC and PTP Hardware Design Example
2.3.2.3. 100GE PCS with Optional RS-FEC Hardware Design Example Components
2.3.2.4. Ethernet Adaptation Flow for 100G (CAUI-2) PAM4 <---> 100G (CAUI-4) NRZ Dynamic Reconfiguration Design Example
3.1.1. Hardware and Software Requirements
3.1.2. Generating the Design
3.1.3. Directory Structure
3.1.4. Simulating the Design Example Testbench
3.1.5. Compiling the Compilation-Only Project
3.1.6. Compiling and Configuring the Design Example in Hardware
3.1.7. Testing the E-tile CPRI PHY Intel® FPGA IP Hardware Design Example
4.1. Quick Start Guide
4.2. 10G/25G Ethernet Dynamic Reconfiguration Design Examples
4.3. 25G Ethernet to CPRI Dynamic Reconfiguration Design Example
4.4. CPRI Dynamic Reconfiguration Design Examples
4.5. 100G Ethernet Dynamic Reconfiguration Design Example
4.6. Document Revision History for the E-Tile Dynamic Reconfiguration Design Example
4.5.1. Functional Description
4.5.2. Testing the 100G Ethernet Dynamic Reconfiguration Hardware Design Example
4.5.3. Simulation Design Examples
4.5.4. 100GE DR Hardware Design Examples
4.5.5. 100G Ethernet Dynamic Reconfiguration Design Example Interface Signals
4.5.6. 100G Ethernet Dynamic Reconfiguration Examples Registers
4.5.7. Steps to Enable FEC
4.5.8. Steps to Disable FEC
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2.3.1.5. E-tile Ethernet IP for Intel Agilex® 7 FPGA 100GE FlexE with Optional RS-FEC Simulation Design Example
The simulation block diagram below is generated using the following settings in the IP parameter editor:
- Under the IP tab:
- Single 100GE with optional RSFEC or 100GE or 1 to 4 channel 10GE/25GE with optional RSFEC and PTP as the core variant.
- 100GE Channel as Active channel(s) at startup if you choose 100GE or 1 to 4 channel 10GE/25GE with optional RSFEC and PTP as the core variant.
- Under the 100GE tab:
- 100G as the Ethernet rate.
- FlexE, FlexE+(528,514)RSFEC, or FlexE+(544,514)RSFEC as the Ethernet IP layer.
Figure 17. Simulation Block Diagram for E-tile Ethernet IP for Intel Agilex® 7 FPGA 100GE FlexE Design Example Block Diagram
The testbench sends traffic through the IP core, exercising the transmit side and receive side of the IP core.
The successful test run displays output confirming the following behavior:
- The client logic resets both the IP cores.
- The stimulus client logic waits for the stimulus RX datapath and FlexE RX datapath to align.
- Once alignment is complete, the stimulus client logic transmits a series of packets to the FlexE IP core.
- The FlexE IP core receives the series of packets and transmits back to the stimulus MAC IP core.
- The stimulus client logic then checks the number of packets received and verify that the packets have no errors.
- Displaying Testbench complete.
The following sample output illustrates a successful simulation test run for a 100GE, FlexE only IP core variation.
# test_dut: def_100G_o_tx_lanes_stable is 1 at time 345685000 # test_dut: waiting for tx_dll_lock.... # dut: o_tx_lanes_stable is 1 at time 345685000 # dut: waiting for tx_dll_lock.... # dut: TX DLL LOCK is 1 at time 398849563 # dut: waiting for tx_transfer_ready.... # dut: TX transfer ready is 1 at time 399169435 # dut: waiting for rx_transfer_ready.... # dut: RX transfer ready is 1 at time 410719813 # dut: EHIP PLD Ready out is 1 at time 410776000 # dut: EHIP reset out is 0 at time 411040000 # dut: EHIP reset ack is 0 at time 412282101 # dut: EHIP TX reset out is 0 at time 413160000 # dut: EHIP TX reset ack is 0 at time 462643731 # dut: waiting for EHIP Ready.... # dut: EHIP READY is 1 at time 462750387 # dut: EHIP RX reset out is 0 at time 463088000 # dut: waiting for rx reset ack.... # dut: EHIP RX reset ack is 0 at time 463283667 # dut: Waiting for RX Block Lock # test_dut: TX DLL LOCK is 1 at time 475452243 # test_dut: waiting for tx_transfer_ready.... # test_dut: TX transfer ready is 1 at time 475772115 # test_dut: waiting for rx_transfer_ready.... # test_dut: RX transfer ready is 1 at time 487164223 # test_dut: EHIP PLD Ready out is 1 at time 487224000 # test_dut: EHIP reset out is 0 at time 487488000 # test_dut: EHIP reset ack is 0 at time 488907771 # test_dut: EHIP TX reset out is 0 at time 489784000 # test_dut: EHIP TX reset ack is 0 at time 539116083 # test_dut: waiting for EHIP Ready.... # test_dut: EHIP READY is 1 at time 539169411 # test_dut: EHIP RX reset out is 0 at time 539512000 # test_dut: waiting for rx reset ack.... # test_dut: EHIP RX reset ack is 0 at time 539702691 # test_dut: Waiting for RX Block Lock # dut: EHIP RX Block Lock is high at time 542102451 # dut: Waiting for AM lock # dut: EHIP RX AM Lock is high at time 543368991 # dut: Waiting for RX alignment # dut: RX deskew locked # dut: RX lane aligmnent locked # dut: ***************************************** # test_dut: EHIP RX Block Lock is high at time 546535341 # test_dut: Waiting for AM lock # test_dut: EHIP RX AM Lock is high at time 547801881 # test_dut: Waiting for RX alignment # test_dut: RX deskew locked # test_dut: RX lane aligmnent locked # test_dut: ** Sending Packet 1... . . . # test_dut: ** Sending Packet 9... # test_dut: ** Sending Packet 10... # test_dut: ** Received Packet 1... . . . # test_dut: ** Received Packet 9... # test_dut: ** Received Packet 10... # test_dut: ** # test_dut: ** Testbench complete. # test_dut: ** # test_dut: *****************************************