Visible to Intel only — GUID: mhs1616342110185
Ixiasoft
Visible to Intel only — GUID: mhs1616342110185
Ixiasoft
1.11.2. Instantiating the Intel Configuration Reset Release Endpoint to Debug Logic IP
You must instantiate the Intel Configuration Reset Release Endpoint to Debug Logic IP in each PR region if multiple PR regions are present in the design. This IP ensures proper function by providing a reset signal to debug logic, such as Signal Tap logic, after partial reconfiguration. This reset signal must be high during configuration, and then this reset signal must go low once partial reconfiguration is complete. You must not release this reset signal after releasing the PR logic reset. The time of this reset release affects the Signal Tap power-up trigger feature. The reset signal must stay low until the next reconfiguration.
If you omit the Intel Configuration Reset Release Endpoint to Debug Logic IP from your PR design, The Compiler issues the following error message:
Error(11176): Alt_sld_fab_1.alt_sld_fab_1.alt_sld_fab_1: The Intel Configuration Reset Release Endpoint to Debug Logic IP must be instantiated to provide the reset signal to the debug logic, such as Signal Tap, etc. after the partial configuration is performed.
Refer to the Intel FPGA Knowledge Database and search for Error 11176 for more information.