Quartus® Prime Pro Edition User Guide: Partial Reconfiguration

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ID 683834
Date 5/16/2025
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Document Table of Contents
Document Table of Contents x
Answers to Top FAQs 1. Creating a Partial Reconfiguration Design 2. Partial Reconfiguration Solutions IP User Guide A. Quartus® Prime Pro Edition User Guides
1. Creating a Partial Reconfiguration Design x
1.1. What's New In This Version 1.2. Partial Reconfiguration Terminology 1.3. Partial Reconfiguration Process Sequence 1.4. Internal Host Partial Reconfiguration 1.5. External Host Partial Reconfiguration 1.6. Partial Reconfiguration Design Flow 1.7. Partial Reconfiguration Design Considerations 1.8. Hierarchical Partial Reconfiguration 1.9. Partial Reconfiguration Design Timing Analysis 1.10. Partial Reconfiguration Design Simulation 1.11. Partial Reconfiguration Design Debugging 1.12. Partial Reconfiguration Security ( Stratix® 10 and Agilex™ 7 Designs) 1.13. PR Bitstream Compression and Encryption ( Arria® 10 and Cyclone® 10 GX Designs) 1.14. Avoiding PR Programming Errors 1.15. Exporting a Version-Compatible Compilation Database for PR Designs 1.16. Creating a Partial Reconfiguration Design Revision History
1.6. Partial Reconfiguration Design Flow x
1.6.1. Step 1: Identify Partial Reconfiguration Resources 1.6.2. Step 2: Create Design Partitions 1.6.3. Step 3: Floorplan the Design 1.6.4. Step 4: Add the Partial Reconfiguration Controller IP 1.6.5. Step 5: Define Personas 1.6.6. Step 6: Create Revisions for Personas 1.6.7. Step 7: Compile the Base Revision and Export the Static Region 1.6.8. Step 8: Setup PR Implementation Revisions 1.6.9. Step 9: Program the FPGA Device
1.6.3. Step 3: Floorplan the Design x
1.6.3.1. Applying Floorplan Constraints Incrementally
1.6.4. Step 4: Add the Partial Reconfiguration Controller IP x
1.6.4.1. Adding the Partial Reconfiguration Controller IP 1.6.4.2. Adding the Partial Reconfiguration Controller Arria® 10/Cyclone 10 IP
1.6.7. Step 7: Compile the Base Revision and Export the Static Region x
1.6.7.1. Understanding PR Logic Utilization Reports
1.6.9. Step 9: Program the FPGA Device x
1.6.9.1. Generating PR Bitstream Files 1.6.9.2. Generating PR Bitstream Files 1.6.9.3. Partial Reconfiguration Bitstream Compatibility Checking 1.6.9.4. Raw Binary Programming File Byte Sequence Transmission Examples 1.6.9.5. Generating a Merged .pmsf File from Multiple .pmsf Files ( Arria® 10 and Cyclone® 10 GX Designs)
1.7. Partial Reconfiguration Design Considerations x
1.7.1. Partial Reconfiguration Design Guidelines 1.7.2. PR Design Timing Closure Best Practices 1.7.3. PR File Management 1.7.4. Evaluating PR Region Initial Conditions 1.7.5. Creating Wrapper Logic for PR Regions 1.7.6. Creating Freeze Logic for PR Regions 1.7.7. Resetting the PR Region Registers 1.7.8. Promoting Global Signals in a PR Region 1.7.9. Planning Clocks and other Global Routing 1.7.10. Implementing Clock Enable for On-Chip Memories
1.7.3. PR File Management x
1.7.3.1. Method 1 (Preferred): Specify Unique Entity and File Names for Each Persona 1.7.3.2. Method 2: Set QSF Assignment for a Parameterized PR Persona
1.7.8. Promoting Global Signals in a PR Region x
1.7.8.1. Viewing Row Clock Region Boundaries
1.7.10. Implementing Clock Enable for On-Chip Memories x
1.7.10.1. Clock Gating
1.8. Hierarchical Partial Reconfiguration x
1.8.1. Using Parent QDB Files from Different Compiles
1.9. Partial Reconfiguration Design Timing Analysis x
1.9.1. Running Timing Analysis on Aggregate Revisions
1.10. Partial Reconfiguration Design Simulation x
1.10.1. Partial Reconfiguration Simulation Flow 1.10.2. Simulating PR Persona Replacement
1.10.2. Simulating PR Persona Replacement x
1.10.2.1. altera_pr_persona_if Module 1.10.2.2. altera_pr_wrapper_mux_out Module 1.10.2.3. altera_pr_wrapper_mux_in Module
1.11. Partial Reconfiguration Design Debugging x
1.11.1. Debugging PR Designs with the Signal Tap Logic Analyzer 1.11.2. Instantiating the Configuration Reset Release Endpoint to Debug Logic IP
1.12. Partial Reconfiguration Security ( Stratix® 10 and Agilex™ 7 Designs) x
1.12.1. PR Bitstream Security Validation ( Stratix® 10 and Agilex™ 7 Designs) 1.12.2. PR Bitstream Authentication ( Stratix® 10 and Agilex™ 7 Designs) 1.12.3. PR Bitstream Encryption ( Stratix® 10 and Agilex™ 7 Designs)
1.13. PR Bitstream Compression and Encryption ( Arria® 10 and Cyclone® 10 GX Designs) x
1.13.1. Generating an Encrypted PR Bitstream ( Arria® 10 or Cyclone® 10 GX Designs) 1.13.2. Clock-to-Data Ratio for Bitstream Encryption and Compression ( Arria® 10 or Cyclone® 10 GX Designs) 1.13.3. Data Compression Comparison
1.15. Exporting a Version-Compatible Compilation Database for PR Designs x
1.15.1. Version-Compatible Database Flow for PR Designs 1.15.2. Generating a Version-Compatible Compilation Database for PR Designs
2. Partial Reconfiguration Solutions IP User Guide x
2.1. Internal and External PR Host Configurations 2.2. Partial Reconfiguration Controller IP 2.3. Partial Reconfiguration Controller Arria® 10/Cyclone® 10 IP 2.4. Partial Reconfiguration External Configuration Controller IP 2.5. Partial Reconfiguration Region Controller IP 2.6. Avalon® -MM Partial Reconfiguration Freeze Bridge IP 2.7. Avalon® -ST Partial Reconfiguration Freeze Bridge IP 2.8. Generating and Simulating Altera* IP 2.9. Quartus® Prime Pro Edition User Guide: Partial Reconfiguration Archive 2.10. Partial Reconfiguration Solutions IP User Guide Revision History
2.2. Partial Reconfiguration Controller IP x
2.2.1. Memory Map 2.2.2. Parameters 2.2.3. Ports 2.2.4. Timing Specifications 2.2.5. PR Error Recovery 2.2.6. Secure Device Manager Firmware Error Reporting
2.2.5. PR Error Recovery x
2.2.5.1. PR Error Recovery Timing Specifications
2.2.6. Secure Device Manager Firmware Error Reporting x
2.2.6.1. SDM Firmware Error Reporting Timing Specification
2.3. Partial Reconfiguration Controller Arria® 10/Cyclone® 10 IP x
2.3.1. Agent Interface 2.3.2. Reconfiguration Sequence 2.3.3. Interrupt Interface 2.3.4. Parameters 2.3.5. Ports 2.3.6. Timing Specifications 2.3.7. PR Control Block and CRC Block Verilog HDL Manual Instantiation 2.3.8. PR Control Block and CRC Block VHDL Manual Instantiation 2.3.9. PR Control Block Signals 2.3.10. Configuring an External Host for Arria® 10 or Cyclone® 10 GX Designs
2.3.4. Parameters x
2.3.4.1. Error Detection CRC Requirements
2.3.8. PR Control Block and CRC Block VHDL Manual Instantiation x
2.3.8.1. PR Control Block and CRC Block VHDL Component Declaration
2.3.9. PR Control Block Signals x
2.3.9.1. PR Control Block Signal Timing Diagrams
2.4. Partial Reconfiguration External Configuration Controller IP x
2.4.1. Parameters 2.4.2. Ports 2.4.3. Partial Reconfiguration External Controller IP Timing Specifications 2.4.4. Configuring an External Host ( Stratix® 10 or Agilex™ FPGA Portfolio Devices)
2.5. Partial Reconfiguration Region Controller IP x
2.5.1. Registers 2.5.2. Parameters 2.5.3. Ports
2.6. Avalon® -MM Partial Reconfiguration Freeze Bridge IP x
2.6.1. Parameters 2.6.2. Interface Ports
2.7. Avalon® -ST Partial Reconfiguration Freeze Bridge IP x
2.7.1. Parameters 2.7.2. Ports
2.8. Generating and Simulating Altera* IP x
2.8.1. Specifying the IP Parameters and Options ( Quartus® Prime Pro Edition) 2.8.2. Running the Freeze Bridge Update script 2.8.3. IP Core Generation Output ( Quartus® Prime Pro Edition) 2.8.4. Arria® 10 and Cyclone® 10 GX PR Control Block Simulation Model 2.8.5. Generating the PR Persona Simulation Model 2.8.6. Secure Device Manager Partial Reconfiguration Simulation Model
2.8.6. Secure Device Manager Partial Reconfiguration Simulation Model x
2.8.6.1. Monitoring the SDM 2.8.6.2. Simulating Unknown Outputs and Persona Activation 2.8.6.3. Simulation RBF Required Word Sequence
Answers to Top FAQs
1. Creating a Partial Reconfiguration Design
2. Partial Reconfiguration Solutions IP User Guide
A. Quartus® Prime Pro Edition User Guides

1.13.2. Clock-to-Data Ratio for Bitstream Encryption and Compression ( Arria® 10 or Cyclone® 10 GX Designs)

The following table lists the valid combinations of bitstream encryption and compression. The Clock-to-Data (CD) ratio is defined as the number of clock cycles that each cycle of data must remain valid before the next clock cycle. For example, a CD ratio of 4 means that the data must remain valid for 4 clock cycles before the next cycle. Enhanced decompression uses the same CD ratio as plain bitstreams (that is, with both encryption and compression off). When enhanced compression is enabled, always refer to x16 data width. If you use compression and enhanced compression together, the CD ratio follows the compression bitstream - 4. If you use plain and enhanced compression together, the CD ratio follows the plain bitstream - 1.
Table 8.  Valid Combinations and CD Ratio for Bitstream Encryption and Compression
Configuration Data Width AES Encryption Basic Compression CD Ratio
x8 Off Off 1
Off On 2
On Off 1
x16 Off Off 1
Off On 4
On Off 2
x32 Off Off 1
Off On 8
On Off 4

Use the exact CD ratio that the Valid combinations and CD Ratio for Bitstream Encryption and Compression table specifies for different bitstream types. The CD ratio for plain .rbf must be 1. The CD ratio for compressed .rbf must be 2, 4 or 8, depending on the width. Do not specify the CD ratio as the necessary minimum to support different bitstream types.

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