Multi Channel DMA Intel® FPGA IP for PCI Express* User Guide

ID 683821
Date 7/30/2024
Public
Document Table of Contents

4.7. Legacy Interrupt Interface

Table 47.  Legacy Interrupt Interface Signals
Signal Name I/O Type Description
p#_app_int_i[7:0] Input

When asserted, these signals indicate an assertion of an INTx message is requested. A transition from high to low indicates a deassertion of the INTx message is requested.

Note: Legacy interrupts are currently not supported by the MCDMA IP. Tie these unused inputs to 0.