Visible to Intel only — GUID: aps1624481800011
Ixiasoft
1. Before You Begin
2. Introduction
3. Functional Description
4. Interface Overview
5. Parameters (H-Tile)
6. Parameters (P-Tile) (F-Tile) (R-Tile)
7. Designing with the IP Core
8. Software Programming Model
9. Registers
10. Troubleshooting/Debugging
11. Multi Channel DMA Intel FPGA IP for PCI Express User Guide Archives
12. Revision History for the Multi Channel DMA Intel FPGA IP for PCI Express User Guide
3.1. Multi Channel DMA
3.2. Bursting Avalon-MM Master (BAM)
3.3. Bursting Avalon-MM Slave (BAS)
3.4. MSI Interrupt
3.5. Config Slave (CS)
3.6. Root Port Address Translation Table Enablement
3.7. Hard IP Reconfiguration Interface
3.8. Config TL Interface
3.9. Configuration Intercept Interface (EP Only)
3.10. Data Mover Only
4.1. Port List
4.2. Clocks
4.3. Resets
4.4. Multi Channel DMA
4.5. Bursting Avalon-MM Master (BAM) Interface
4.6. Bursting Avalon-MM Slave (BAS) Interface
4.7. Legacy Interrupt Interface
4.8. MSI Interface
4.9. Config Slave Interface (RP only)
4.10. Hard IP Reconfiguration Interface
4.11. Config TL Interface
4.12. Configuration Intercept Interface (EP Only)
4.13. Data Mover Interface
4.14. Hard IP Status Interface
4.15. Precision Time Management (PTM) Interface
8.1.6.1. ifc_api_start
8.1.6.2. ifc_mcdma_port_by_name
8.1.6.3. ifc_qdma_device_get
8.1.6.4. ifc_num_channels_get
8.1.6.5. ifc_qdma_channel_get
8.1.6.6. ifc_qdma_acquire_channels
8.1.6.7. ifc_qdma_release_all_channels
8.1.6.8. ifc_qdma_device_put
8.1.6.9. ifc_qdma_channel_put
8.1.6.10. ifc_qdma_completion_poll
8.1.6.11. ifc_qdma_request_start
8.1.6.12. ifc_qdma_request_prepare
8.1.6.13. ifc_qdma_descq_queue_batch_load
8.1.6.14. ifc_qdma_request_submit
8.1.6.15. ifc_qdma_pio_read32
8.1.6.16. ifc_qdma_pio_write32
8.1.6.17. ifc_qdma_pio_read64
8.1.6.18. ifc_qdma_pio_write64
8.1.6.19. ifc_qdma_pio_read128
8.1.6.20. ifc_qdma_pio_write128
8.1.6.21. ifc_qdma_pio_read256
8.1.6.22. ifc_qdma_pio_write256
8.1.6.23. ifc_request_malloc
8.1.6.24. ifc_request_free
8.1.6.25. ifc_app_stop
8.1.6.26. ifc_qdma_poll_init
8.1.6.27. ifc_qdma_poll_add
8.1.6.28. ifc_qdma_poll_wait
8.1.6.29. ifc_mcdma_port_by_name
Visible to Intel only — GUID: aps1624481800011
Ixiasoft
2.1.1. Endpoint Mode
- MCDMA P-Tile: PCIe Gen4/Gen3 x16/x8 and 2x8 ports in Stratix® 10 DX and Agilex™ 7 devices.
- MCDMA H-Tile: PCIe Gen3 x16/x8 in Stratix® 10 GX and Stratix® 10 MX devices.
- MCDMA F-Tile: PCIe Gen4/Gen3 x16/x8/x4 and 2x8 ports in Agilex™ 7 device
- MCDMA R-Tile:
- PCIe Gen5/Gen4/Gen3 2x8 in Agilex™ 7 devices.
- PCIe Gen4/Gen3 x16 only in Agilex™ 7 I-Series FPGA Development Kit DK-DEV-AGI027R1BES R-Tile B0 revision.
- PCIe Gen5/Gen4/Gen3 4x4 only in Agilex™ 7 I-Series FPGA Development Kit DK-DEV- AGI027R1BES R-Tile B0 revision. Port 2 and 3 don't support SRIOV, FLR, user event MSI-X and MSI capability. Port 2 and 3 only support BAM, BAS and BAM+BAS user mode.
- User Mode options:
- Multi Channel DMA
- Bursting Avalon Master (BAM)
- Bursting Avalon Slave (BAS)
- BAM and BAS
- BAM and MCDMA
- Data Mover Only (not available in MCDMA R/P/F-Tile IP x4 and MCDMA H-Tile IP)
- BAM, BAS and MCDMA
- Supports up to 2K DMA channels.
Table 2. Maximum DMA channels Device MCDMA Interface Type AVMM AVST Stratix® 10 GX
Stratix® 10 MX
Stratix® 10 DX
Agilex™ 7
2048* 2048* Note: * = Maximum 512 channels per Function - Per Descriptor completion notification with MSI-X or Writebacks
- Option to select Avalon-MM or Avalon-ST DMA for user logic interface
- SR-IOV
- User MSI-X in MCDMA mode (Not supported in R-Tile MCDMA IP x4 Endpoint Ports 2 and 3)
- User FLR in MCDMA mode (Not supported in R-Tile MCDMA IP x4 Endpoint Ports 2 and 3)
- 10-bit tag feature
- Supports Precision Time Measurement (PTM). (Only available for R-Tile MCDMA IP Endpoint Ports 0 and 1)
- MSI Interrupt in BAS (only available for for all H/R/F/P Tiles MCDMA IP). It is not supported in R-Tile MCDMA IP x4 Endpoint Ports 2 and 3)
- H2D address and payload size alignment to byte granularity for AVST
- Ports subdivided 2x8 can run independently and concurrently (separately) instances on MCDMA and AVMM IP for P-Tile MCDMA Stratix® 10 DX and R-Tile MCDMA Agilex™ 7 devices.
- Example: Port0 -> MCDMA AVMMDMA DE & Port1 -> BAM+MCDMA Pkt Gen Checker DE.
- Each instance runs independently with separate PERST
- SCTH support
- Ports subdivided 4x4 can run independently and concurrently (separately) instances on MCDMA and AVMM IP for R-Tile MCDMA Intel Agilex 7 devices.
- Examples: Port0 -> MCDMA, Port1 -> BAM+MCDMA, Port2 -> BAS & Port3 -> BAM+BAS.
- Each instance runs independently with separate PERST
- Only SCT support
- Example Design Simulation is only supported on Port0. Simulation is not support on Port0, Port1 and Port2
- Maximum payload size supported:
- Stratix® 10 GX and Stratix® 10 MX devices: 512 bytes
- Stratix® 10 DX and Agilex™ 7 devices: 512 / 256 / 128 bytes