Multi Channel DMA Intel® FPGA IP for PCI Express* User Guide

ID 683821
Date 7/30/2024
Public
Document Table of Contents

2.1.1. Endpoint Mode

  • MCDMA P-Tile: PCIe Gen4/Gen3 x16/x8 and 2x8 ports in Stratix® 10 DX and Agilex™ 7 devices.
  • MCDMA H-Tile: PCIe Gen3 x16/x8 in Stratix® 10 GX and Stratix® 10 MX devices.
  • MCDMA F-Tile: PCIe Gen4/Gen3 x16/x8/x4 and 2x8 ports in Agilex™ 7 device
  • MCDMA R-Tile:
    • PCIe Gen5/Gen4/Gen3 2x8 in Agilex™ 7 devices.
    • PCIe Gen4/Gen3 x16 only in Agilex™ 7 I-Series FPGA Development Kit DK-DEV-AGI027R1BES R-Tile B0 revision.
    • PCIe Gen5/Gen4/Gen3 4x4 only in Agilex™ 7 I-Series FPGA Development Kit DK-DEV- AGI027R1BES R-Tile B0 revision. Port 2 and 3 don't support SRIOV, FLR, user event MSI-X and MSI capability. Port 2 and 3 only support BAM, BAS and BAM+BAS user mode.
  • User Mode options:
    • Multi Channel DMA
    • Bursting Avalon Master (BAM)
    • Bursting Avalon Slave (BAS)
    • BAM and BAS
    • BAM and MCDMA
    • Data Mover Only (not available in MCDMA R/P/F-Tile IP x4 and MCDMA H-Tile IP)
    • BAM, BAS and MCDMA
  • Supports up to 2K DMA channels.
    Table 2.  Maximum DMA channels
    Device MCDMA Interface Type
    AVMM AVST

    Stratix® 10 GX

    Stratix® 10 MX

    Stratix® 10 DX

    Agilex™ 7

    2048* 2048*
    Note: * = Maximum 512 channels per Function
  • Per Descriptor completion notification with MSI-X or Writebacks
  • Option to select Avalon-MM or Avalon-ST DMA for user logic interface
  • SR-IOV
  • User MSI-X in MCDMA mode (Not supported in R-Tile MCDMA IP x4 Endpoint Ports 2 and 3)
  • User FLR in MCDMA mode (Not supported in R-Tile MCDMA IP x4 Endpoint Ports 2 and 3)
  • 10-bit tag feature
  • Supports Precision Time Measurement (PTM). (Only available for R-Tile MCDMA IP Endpoint Ports 0 and 1)
  • MSI Interrupt in BAS (only available for for all H/R/F/P Tiles MCDMA IP). It is not supported in R-Tile MCDMA IP x4 Endpoint Ports 2 and 3)
  • H2D address and payload size alignment to byte granularity for AVST
  • Ports subdivided 2x8 can run independently and concurrently (separately) instances on MCDMA and AVMM IP for P-Tile MCDMA Stratix® 10 DX and R-Tile MCDMA Agilex™ 7 devices.
    • Example: Port0 -> MCDMA AVMMDMA DE & Port1 -> BAM+MCDMA Pkt Gen Checker DE.
    • Each instance runs independently with separate PERST
    • SCTH support
  • Ports subdivided 4x4 can run independently and concurrently (separately) instances on MCDMA and AVMM IP for R-Tile MCDMA Intel Agilex 7 devices.
    • Examples: Port0 -> MCDMA, Port1 -> BAM+MCDMA, Port2 -> BAS & Port3 -> BAM+BAS.
    • Each instance runs independently with separate PERST
    • Only SCT support
  • Example Design Simulation is only supported on Port0. Simulation is not support on Port0, Port1 and Port2
  • Maximum payload size supported:
    • Stratix® 10 GX and Stratix® 10 MX devices: 512 bytes
    • Stratix® 10 DX and Agilex™ 7 devices: 512 / 256 / 128 bytes