Quartus® Prime Pro Edition User Guide: Debug Tools

ID 683819
Date 6/09/2025
Public

Visible to Intel only — GUID: mte1492824571808

Ixiasoft

Document Table of Contents

2.10.2.2.2. Preparing the Base Revision for Signal Tap Debugging

In the base revision, for each PR region that you want to debug in the design:

  1. Instantiate the SLD JTAG Bridge Agent Altera IP in the static region.
  2. Instantiate the SLD JTAG Bridge Host Altera IP in the PR region of the default persona.

You can use the IP Catalog or Platform Designer to instantiate SLD JTAG Bridge components.