SDI II Intel® Cyclone 10 GX FPGA IP Design Example User Guide

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ID 683815
Date 12/12/2022
Public
Document Table of Contents
Document Table of Contents x
1. SDI II Intel FPGA IP Design Example Quick Start Guide 2. SDI II Intel FPGA IP Design Example Detailed Description 3. SDI II Intel® Cyclone® 10 GX FPGA IP Design Example User Guide Archives 4. Revision History for SDI II Intel® Cyclone® 10 GX FPGA IP Design Example User Guide
1. SDI II Intel FPGA IP Design Example Quick Start Guide x
1.1. Directory Structure 1.2. Hardware and Software Requirements 1.3. Generating the Design 1.4. Simulating the Design 1.5. Compiling and Testing the Design 1.6. SDI II Intel FPGA Design Example Parameters
1.5. Compiling and Testing the Design x
1.5.1. Connection and Settings Guidelines 1.5.2. Design Considerations
1.6. SDI II Intel FPGA Design Example Parameters x
1.6.1. Design Example Presets
2. SDI II Intel FPGA IP Design Example Detailed Description x
2.1. Parallel Loopback Design Examples 2.2. Serial Loopback Design Examples 2.3. Design Components 2.4. Clocking Scheme Signals 2.5. Interface Signals 2.6. Video Pattern Generator Parameters 2.7. Hardware Setup 2.8. Simulation Testbench
1. SDI II Intel FPGA IP Design Example Quick Start Guide
2. SDI II Intel FPGA IP Design Example Detailed Description
3. SDI II Intel® Cyclone® 10 GX FPGA IP Design Example User Guide Archives
4. Revision History for SDI II Intel® Cyclone® 10 GX FPGA IP Design Example User Guide

1.2. Hardware and Software Requirements

Intel uses the following hardware and software to test the design examples.

Hardware

  • Intel® Cyclone® 10 GX FPGA Development Kit
  • SDI Signal Generator
  • SDI Signal Analyzer
  • Bayonet Neill–Concelman (BNC) to BNC cables
  • Nextera VIDIO* FMC Development Module VIDIO-12G-A (Nextera 12G SDI FMC daughter card)

Software

  • Intel® Quartus® Prime Pro Edition (for hardware testing)
  • Questa* Intel® FPGA Edition, ModelSim SE*, Riviera-PRO* , VCS* (Verilog HDL only)/ VCS* MX, or Xcelium* Parallel simulator
Level Two Title