F-Tile Ethernet Intel® FPGA Hard IP Design Example User Guide

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ID 683804
Date 12/04/2023
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Document Table of Contents
Document Table of Contents x
1. Quick Start Guide 2. Design Example: Single IP Core Instantiation 3. Design Example: Single IP Core Instantiation with Precision Time Protocol 4. Design Example: Single IP Core Instantiation with Auto-Negotiation and Link Training 5. Design Example: Multiple IP Core Instantiation 6. Design Example: Two Separate Instances of Auto-Negotiation and Link Training and Ethernet IP Design 7. F-Tile Ethernet Intel® FPGA Hard IP Design Example User Guide Archives 8. Document Revision History for the F-Tile Ethernet Intel FPGA Hard IP Design Example User Guide
1. Quick Start Guide x
1.1. Generating the Design 1.2. Directory Structure 1.3. Simulating the Design Example Testbench 1.4. Hardware and Software Requirements 1.5. Compiling and Configuring the Design Example in Hardware 1.6. Testing the F-Tile Ethernet Intel FPGA Hard IP Hardware Design Example 1.7. Register Maps
1.1. Generating the Design x
1.1.1. Generating Single IP Instance Design 1.1.2. Generating Two Separate Instances of IP Design 1.1.3. Generating Multiple IP Instance Design
1.3. Simulating the Design Example Testbench x
1.3.1. Fast Sim Model for FGT Variants 1.3.2. Fast Sim Model for FHT Variants
2. Design Example: Single IP Core Instantiation x
2.1. Features 2.2. Functional Description 2.3. Simulation 2.4. Packet Client Registers
2.2. Functional Description x
2.2.1. Variation: F-Tile Ethernet Intel FPGA Hard IP with FHT PMA
2.3. Simulation x
2.3.1. Simulation Testbench Flow for MAC Mode 2.3.2. Simulation Testbench Flow for PCS, OTN, and FlexE Modes
3. Design Example: Single IP Core Instantiation with Precision Time Protocol x
3.1. Features 3.2. Functional Description 3.3. Simulation 3.4. Hardware Design Example 3.5. Registers
4. Design Example: Single IP Core Instantiation with Auto-Negotiation and Link Training x
4.1. Features 4.2. Functional Description 4.3. Simulation 4.4. QSF Assignments 4.5. Hardware Design Example
5. Design Example: Multiple IP Core Instantiation x
5.1. Features 5.2. Functional Description 5.3. Simulation
6. Design Example: Two Separate Instances of Auto-Negotiation and Link Training and Ethernet IP Design x
6.1. Features 6.2. Functional Description 6.3. Simulation 6.4. QSF Assignments 6.5. Hardware Design Example
1. Quick Start Guide
2. Design Example: Single IP Core Instantiation
3. Design Example: Single IP Core Instantiation with Precision Time Protocol
4. Design Example: Single IP Core Instantiation with Auto-Negotiation and Link Training
5. Design Example: Multiple IP Core Instantiation
6. Design Example: Two Separate Instances of Auto-Negotiation and Link Training and Ethernet IP Design
7. F-Tile Ethernet Intel® FPGA Hard IP Design Example User Guide Archives
8. Document Revision History for the F-Tile Ethernet Intel FPGA Hard IP Design Example User Guide

1.3.1. Fast Sim Model for FGT Variants

To provide a reduction in a real-time simulation duration, you can utilize a Fast Sim model in your design example testbench. For FGT variants, the model is enabled by a macro in the simulation run script.
To enable the Fast Sim model, add the following macro to your simulation run script: 
+define+IP7581SERDES_UX_SIMSPEED
The design example simulation script enables the macro by default for all variants with the exception of variant auto-negotiation and link training.
  • In PTP variants, an additional switch must be defined a shown below.
    +define+UX_WORD_CLK_DRIFT_CORRECTION
    This switch enables the corrections for timestamp accuracy issues in the FGT fast sim model.
    Note: The FGT Fast Sim Model with PTP enabled can support up to 10,000 μs simulation time. If you run the simulation beyond this point, the simulation behaves unpredictably. This limitation is only for sim model.
  • The macro is not available for designs with enabled auto-negotiation and link training
  • You can achieve faster simulation times with auto-negotiation and link training enabled designs by running i_reconfig_clk at 10GHz. Furthermore, you can skip auto-negotiation and link training functionality and go directly to Data/Ethernet mode by writing to auto-negotiation and link training Control Status Registers (CSRs) or GUI parameters.

You can also add the macro to your simulation script for your own testbench.

Attention: In 53G PAM4 Ethernet IPs, you must set the serial clock input to the IP to the exact value of 37.648 ps for simulation to work correctly. This limitation does not apply to the design example simulations since the serial lines are in a loopback.
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