F-Tile Ethernet Intel® FPGA Hard IP Design Example User Guide

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ID 683804
Date 9/26/2022
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Document Table of Contents
Document Table of Contents x
1. Quick Start Guide 2. Design Example: Single IP Core Instantiation 3. Design Example: Single IP Core Instantiation with Precision Time Protocol 4. Design Example: Single IP Core Instantiation with Auto-Negotiation and Link Training 5. Design Example: Multiple IP Core Instantiation 6. F-Tile Ethernet Intel® FPGA Hard IP Design Example User Guide Archives 7. Document Revision History for the F-Tile Ethernet Intel FPGA Hard IP Design Example User Guide
1. Quick Start Guide x
1.1. Generating the Design 1.2. Directory Structure 1.3. Generating Tile Files 1.4. Simulating the Design Example Testbench 1.5. Hardware and Software Requirements 1.6. Compiling and Configuring the Design Example in Hardware 1.7. Testing the F-Tile Ethernet Intel FPGA Hard IP Hardware Design Example 1.8. Register Maps
1.1. Generating the Design x
1.1.1. Generating Single IP Instance Design 1.1.2. Generating Multiple IP Instance Design
1.4. Simulating the Design Example Testbench x
1.4.1. Fast Sim Model for FGT Variants
2. Design Example: Single IP Core Instantiation x
2.1. Features 2.2. Functional Description 2.3. Simulation 2.4. Packet Client Registers
2.2. Functional Description x
2.2.1. Variation: F-Tile Ethernet Intel FPGA Hard IP with FHT PMA
2.3. Simulation x
2.3.1. Simulation Testbench Flow for MAC Mode 2.3.2. Simulation Testbench Flow for PCS, OTN, and FlexE Modes
3. Design Example: Single IP Core Instantiation with Precision Time Protocol x
3.1. Features 3.2. Functional Description 3.3. Simulation 3.4. Hardware Design Example 3.5. Registers
4. Design Example: Single IP Core Instantiation with Auto-Negotiation and Link Training x
4.1. Features 4.2. Functional Description 4.3. Simulation 4.4. QSF Assignments 4.5. Hardware Design Example
5. Design Example: Multiple IP Core Instantiation x
5.1. Features 5.2. Functional Description 5.3. Simulation
1. Quick Start Guide
2. Design Example: Single IP Core Instantiation
3. Design Example: Single IP Core Instantiation with Precision Time Protocol
4. Design Example: Single IP Core Instantiation with Auto-Negotiation and Link Training
5. Design Example: Multiple IP Core Instantiation
6. F-Tile Ethernet Intel® FPGA Hard IP Design Example User Guide Archives
7. Document Revision History for the F-Tile Ethernet Intel FPGA Hard IP Design Example User Guide

1.3. Generating Tile Files

The Support-Logic Generation is a pre-synthesis step used to generate tile-related files required for simulation and hardware design. The tile generation is required for all F-tile based design simulations. You must complete this step before simulation.

Starting with Intel® Quartus® Prime software version 21.4, the Support-Logic Generation command is run automatically when you generate your design using F-Tile Ethernet Intel FPGA Hard IP Parameter Editor.

Otherwise, use GUI or command prompt window to perform the tile generation.
  • Using Graphical User Interface:
    1. In the Intel® Quartus® Prime Pro Edition, navigate to the Compilation Dashboard window for your project overview.
    2. Click Support-Logic Generation.
  • Using command prompt window:
    1. At the command prompt, navigate to the hardware_test_design folder in your example design:
      cd <your_design_path>/hardware_test_design
    2. If you enabled auto-negotiation and link training, you must specify the pin assignments. Append the eth_f_hw.qsf file with the recommended pin location assignments described in QSF Assignments.
      Note: This step is required only when you enabled the AN/LT feature in the F-Tile Ethernet Intel FPGA Hard IP and instantiated the F-Tile Ethernet Intel® FPGA IP.
    3. Run the following command:
      quartus_tlg eth_f_hw

This step generates eth_f_hw_tiles files. The generated files are located in the <your_design>/hardware_test_design directory and contain the full netlist for simulation and synthesis.

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