Intel® Agilex™ F-Series and I-Series General-Purpose I/O User Guide

ID 683780
Date 9/29/2022
Public

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Document Table of Contents

6.1.5.1.2. Output and Output Enable Paths

The output delay element sends data to the pad through the output buffer.

Each output path contains two stages of DDIOs, which are half-rate and full-rate.

Figure 36. Simplified View of Single-Ended GPIO Output Path


Figure 37. Output Path Waveform in DDIO Mode with Half-Rate Conversion
Figure 38.  Simplified View of Output Enable Path


The difference between the output path and output enable (OE) path is that the OE path does not contain full-rate DDIO. To support packed-register implementations in the OE path, a simple register operates as full-rate DDIO. For the same reason, only one half-rate DDIO is present.

The OE path operates in the following three fundamental modes:

  • Bypass—the core sends data directly to the delay element, bypassing all DDIOs.
  • Packed Register—bypasses half-rate DDIO.
  • SDR output at half-rate—half-rate DDIOs convert data from full-rate to half-rate.
Note: The GPIO IP does not support dynamic calibration of bidirectional pins.