ALTPLL (Phase-Locked Loop) IP Core User Guide

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ID 683732
Date 6/16/2017
Public
Document Table of Contents
Document Table of Contents x
ALTPLL (Phase-Locked Loop) IP Core User Guide
ALTPLL (Phase-Locked Loop) IP Core User Guide x
ALTPLL Features Ports and Parameters Design Examples Document Revision History
ALTPLL Features x
Phase-Locked Loop Types of PLLs Operation Modes Output Clocks Advanced Features PLL Output Counter Cascading
Phase-Locked Loop x
Building Blocks of a PLL PLL Behavior
Types of PLLs x
Parameter Setting Total Number of PLL Available in Each Supported Device Family
Operation Modes x
Operation Modes Supported in Each Device Family Parameter Settings Determining the PLL Lock Range Expanding the PLL Lock Range Setting Up Stratix III and Stratix IV PLLs for LVDS Interfacing Simulating External Feedback Board Delay
Output Clocks x
Parameter Settings Parameter Settings When “Set up PLL in LVDS mode” Option is Enabled Summary of PLL Output Clocks
Advanced Features x
Advanced Control Signals (pllena, areset, pfdena) Clock Switchover Spread-Spectrum Clocking Gated Lock and Self-Reset Programmable Bandwidth Advanced PLL Parameters PLL Dynamic Reconfiguration Dynamic Phase Configuration
Advanced Control Signals (pllena, areset, pfdena) x
pllena areset pfdena Parameter Settings Summary of Advanced Control Signals
Clock Switchover x
Parameter Settings Summary of Automatic Clock Switchover Feature
Spread-Spectrum Clocking x
Parameter Settings Summary of Spread-Spectrum Clocking Feature
Gated Lock and Self-Reset x
Gated Lock Self-Reset on Loss of Lock Parameter Settings Calculating the Value of Gated Lock Counter Summary of Gated Lock Signals and Self-Reset on Loss of Lock
Programmable Bandwidth x
Parameter Settings Summary of Programmable Bandwidth Support
Advanced PLL Parameters x
Advanced Parameter Settings
PLL Dynamic Reconfiguration x
Parameter Settings Summary of Supported Device Families for PLL Dynamic Reconfiguration Feature
Dynamic Phase Configuration x
Supported Devices Parameter Settings Modifying the PLL Phase Shift Step Resolution Using Advanced Parameters
Ports and Parameters x
ALTPLL Input Ports ALTPLL Output Ports ALTPLL Bidirectional Port ALTPLL Parameters
Design Examples x
Design Files Design Example 1: Differential Clock Design Example 2: Generating Clock Signals
Design Example 1: Differential Clock x
Generating a 166-MHz Differential SSTL External Clock Implementing the ddr_clk Design Functional Results — Simulate the ddr_clk Design in the ModelSim®-Altera Software
Design Example 2: Generating Clock Signals x
Generating 133-MHz, 200-MHz, and 200-MHz Time-Shifted Clocks Implementing the shift_clk Design Simulating the shift_clk Design in the ModelSim-Altera Software
ALTPLL (Phase-Locked Loop) IP Core User Guide

Simulating External Feedback Board Delay

The PLL external feedback board delay option is available for Arria GX, Cyclone, HardCopy series, Stratix, Stratix GX, Stratix II, and Stratix II GX device families only.

The functional and timing models of these devices do not support the simulation of external feedback. To simulate the external feedback mode, perform the following steps:

  1. In the Quartus® Prime software, open an existing project or create a new project.
  2. On the Assignments menu, click Assignment Editor.
  3. In the Category bar, under Timing, click All.
  4. In the spreadsheet, double-click an empty row in the To cell and either type in the pin name or click the arrow to use the Node Finder to search for the external feedback input pin.
  5. Double-click the Assignment Name cell, and select PLL External Feedback Board Delay.
  6. In the Value cell, double-click and type the amount of time for the signal to propagate between the external clock output pin through the trace on the board and into the external feedback input pin.
  7. Simulate your design.
The behavioral models for the ALTPLL IP core reside in the \quartus\eda\sim_lib directory. The altera_mf.vhd file contains the VHDL behavioral models and the altera_mf.v file contains the Verilog HDL behavioral models. The behavioral model does not perform parameter error checking, so you must specify valid values.
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