ALTPLL (Phase-Locked Loop) IP Core User Guide

ID 683732
Date 6/16/2017
Public
Document Table of Contents

Setting Up Stratix III and Stratix IV PLLs for LVDS Interfacing

The ALTLVDS IP core provides SERDES transmitter and receiver functionality commonly used in LVDS interfacing.

The following table lists the options and values to configure a PLL on a Stratix III or Stratix IV device to clock an ALTLVDS IP core.

Table 5.  Options to Configure a PLL on a Stratix III or Stratix IV Device

Option

Value

Which PLL type will you be using?

Left_Right PLL

How will the PLL outputs be generated?

In Source-Synchronous Compensation mode

On the Output clocks page

c0

This clock signal is the high-speed serial clock (fast clock) signal connected to the rx_inclock or tx_inclock port of the ALTLVDS IP core.

Output frequency = data rate

Phase shift = -180 degrees

Duty cycle = 50%

c1

This clock signal is the load enable signal connected to the rx_enable or tx_enable port of the ALTLVDS IP core.

Output frequency = data rate/deserialization factor

Phase shift = [(deserialization factor – 2)/deserialization factor] × 360 degrees

Duty cycle = (100/deserialization factor)%

c2

This clock signal is the slow clock signal that feeds the synchronization register of the ALTLVDS IP core.

Output frequency = data rate/deserialization factor

Phase shift = (-180/deserialization factor) degrees

Duty cycle = 50%