ALTPLL (Phase-Locked Loop) IP Core User Guide

ID 683732
Date 6/16/2017
Public
Document Table of Contents

Parameter Settings When “Set up PLL in LVDS mode” Option is Enabled

The following parameter settings apply only when Set up PLL in LVDS Mode is turned on for Arria GX, Stratix II, Stratix II GX, and HardCopy II fast PLLs.

When you turn on Set up PLL in LVDS mode, two additional options are available on the Output Clocks pages for c0 and c1.

The following figure shows the additional options to configure the c0 output clock signal.

Figure 6. Additional Options to Configure the c0 Output Clock Signal


Turn on Create sclkout0/enable0 outputs to create the sclkout0 and enable0 ports. The sclkout0 port is the serial clock output port, and the enable0 port is the enable port.

The following figure shows the additional options to configure the c0 output clock signal.

Figure 7. Sclkout Phase Shift Option


The sclkout phase shift option allows you to edit the phase shift of the sclkout signal (in this case, the sclkout0 signal).

Only two pairs of sclkout and enable ports can be created in an ALTPLL IP core. The sclkout0 and enable0 ports are for the c0 output clock, and the sclkout1 and enable1 ports are for the c1 output clock.