ALTPLL (Phase-Locked Loop) IP Core User Guide

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ID 683732
Date 6/16/2017
Public
Document Table of Contents
Document Table of Contents x
ALTPLL (Phase-Locked Loop) IP Core User Guide
ALTPLL (Phase-Locked Loop) IP Core User Guide x
ALTPLL Features Ports and Parameters Design Examples Document Revision History
ALTPLL Features x
Phase-Locked Loop Types of PLLs Operation Modes Output Clocks Advanced Features PLL Output Counter Cascading
Phase-Locked Loop x
Building Blocks of a PLL PLL Behavior
Types of PLLs x
Parameter Setting Total Number of PLL Available in Each Supported Device Family
Operation Modes x
Operation Modes Supported in Each Device Family Parameter Settings Determining the PLL Lock Range Expanding the PLL Lock Range Setting Up Stratix III and Stratix IV PLLs for LVDS Interfacing Simulating External Feedback Board Delay
Output Clocks x
Parameter Settings Parameter Settings When “Set up PLL in LVDS mode” Option is Enabled Summary of PLL Output Clocks
Advanced Features x
Advanced Control Signals (pllena, areset, pfdena) Clock Switchover Spread-Spectrum Clocking Gated Lock and Self-Reset Programmable Bandwidth Advanced PLL Parameters PLL Dynamic Reconfiguration Dynamic Phase Configuration
Advanced Control Signals (pllena, areset, pfdena) x
pllena areset pfdena Parameter Settings Summary of Advanced Control Signals
Clock Switchover x
Parameter Settings Summary of Automatic Clock Switchover Feature
Spread-Spectrum Clocking x
Parameter Settings Summary of Spread-Spectrum Clocking Feature
Gated Lock and Self-Reset x
Gated Lock Self-Reset on Loss of Lock Parameter Settings Calculating the Value of Gated Lock Counter Summary of Gated Lock Signals and Self-Reset on Loss of Lock
Programmable Bandwidth x
Parameter Settings Summary of Programmable Bandwidth Support
Advanced PLL Parameters x
Advanced Parameter Settings
PLL Dynamic Reconfiguration x
Parameter Settings Summary of Supported Device Families for PLL Dynamic Reconfiguration Feature
Dynamic Phase Configuration x
Supported Devices Parameter Settings Modifying the PLL Phase Shift Step Resolution Using Advanced Parameters
Ports and Parameters x
ALTPLL Input Ports ALTPLL Output Ports ALTPLL Bidirectional Port ALTPLL Parameters
Design Examples x
Design Files Design Example 1: Differential Clock Design Example 2: Generating Clock Signals
Design Example 1: Differential Clock x
Generating a 166-MHz Differential SSTL External Clock Implementing the ddr_clk Design Functional Results — Simulate the ddr_clk Design in the ModelSim®-Altera Software
Design Example 2: Generating Clock Signals x
Generating 133-MHz, 200-MHz, and 200-MHz Time-Shifted Clocks Implementing the shift_clk Design Simulating the shift_clk Design in the ModelSim-Altera Software
ALTPLL (Phase-Locked Loop) IP Core User Guide

Parameter Settings

The parameter settings to configure the bandwidth of the ALTPLL IP core are located on the Bandwidth/SS page of the ALTPLL parameter editor.

The following figure shows the bandwidth configuration options on the Bandwidth/SS page.

Figure 14. Bandwidth Configuration Options


The following list describes the preset values that you can choose:

  • Low—PLL with a low bandwidth has better jitter rejection but a slower lock time.
  • High—PLL with a high bandwidth has a faster lock time but tracks more jitter.
  • Medium—A medium bandwidth offers a balance between lock time and jitter rejection.

If you select Auto, the ALTPLL parameter editor chooses the best possible bandwidth values to achieve the desired PLL settings. In some cases, you can get a bandwidth value outside the Low and High preset range.

To set the bandwidth manually, select Custom, and specify the value. The compiler attempts to achieve the value that you specify, or the closest possible value to achieve your desired setting. You can check the bandwidth value in the compilation report.

The table on the right in the Bandwidth/SS page shows the values of the charge pump current, loop filter resistance and capacitance, and the M counter.

An advanced level of control is also possible for precise control of the PLL loop filter characteristics. This level allows you to select the charge pump current, and loop filter resistance and capacitance values explicitly. The advanced parameters are: charge_pump_current, loop_filter_r, and loop_filter_c.

You can use the programmable bandwidth feature with the clock switchover or spread-spectrum features to get the PLL output settings that you desire. You must set the bandwidth to Auto if you want to enable the spread-spectrum feature.

These parameter settings create no additional top-level ports.

Level Two Title