ALTPLL (Phase-Locked Loop) IP Core User Guide

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ID 683732
Date 6/16/2017
Public
Document Table of Contents
Document Table of Contents x
ALTPLL (Phase-Locked Loop) IP Core User Guide
ALTPLL (Phase-Locked Loop) IP Core User Guide x
ALTPLL Features Ports and Parameters Design Examples Document Revision History
ALTPLL Features x
Phase-Locked Loop Types of PLLs Operation Modes Output Clocks Advanced Features PLL Output Counter Cascading
Phase-Locked Loop x
Building Blocks of a PLL PLL Behavior
Types of PLLs x
Parameter Setting Total Number of PLL Available in Each Supported Device Family
Operation Modes x
Operation Modes Supported in Each Device Family Parameter Settings Determining the PLL Lock Range Expanding the PLL Lock Range Setting Up Stratix III and Stratix IV PLLs for LVDS Interfacing Simulating External Feedback Board Delay
Output Clocks x
Parameter Settings Parameter Settings When “Set up PLL in LVDS mode” Option is Enabled Summary of PLL Output Clocks
Advanced Features x
Advanced Control Signals (pllena, areset, pfdena) Clock Switchover Spread-Spectrum Clocking Gated Lock and Self-Reset Programmable Bandwidth Advanced PLL Parameters PLL Dynamic Reconfiguration Dynamic Phase Configuration
Advanced Control Signals (pllena, areset, pfdena) x
pllena areset pfdena Parameter Settings Summary of Advanced Control Signals
Clock Switchover x
Parameter Settings Summary of Automatic Clock Switchover Feature
Spread-Spectrum Clocking x
Parameter Settings Summary of Spread-Spectrum Clocking Feature
Gated Lock and Self-Reset x
Gated Lock Self-Reset on Loss of Lock Parameter Settings Calculating the Value of Gated Lock Counter Summary of Gated Lock Signals and Self-Reset on Loss of Lock
Programmable Bandwidth x
Parameter Settings Summary of Programmable Bandwidth Support
Advanced PLL Parameters x
Advanced Parameter Settings
PLL Dynamic Reconfiguration x
Parameter Settings Summary of Supported Device Families for PLL Dynamic Reconfiguration Feature
Dynamic Phase Configuration x
Supported Devices Parameter Settings Modifying the PLL Phase Shift Step Resolution Using Advanced Parameters
Ports and Parameters x
ALTPLL Input Ports ALTPLL Output Ports ALTPLL Bidirectional Port ALTPLL Parameters
Design Examples x
Design Files Design Example 1: Differential Clock Design Example 2: Generating Clock Signals
Design Example 1: Differential Clock x
Generating a 166-MHz Differential SSTL External Clock Implementing the ddr_clk Design Functional Results — Simulate the ddr_clk Design in the ModelSim®-Altera Software
Design Example 2: Generating Clock Signals x
Generating 133-MHz, 200-MHz, and 200-MHz Time-Shifted Clocks Implementing the shift_clk Design Simulating the shift_clk Design in the ModelSim-Altera Software
ALTPLL (Phase-Locked Loop) IP Core User Guide

Parameter Settings

The Output Clocks page of the ALTPLL parameter editor contains the parameter settings for the clock output signals. The output clock port can be used as a core output clock or an external output clock port. The core output clock is used to feed the FPGA core and the external output clock is used to feed the dedicated pins on the FPGA.

The following figure shows a screenshot of the page to configure the c0 clock output signal of the ALTPLL IP core.

Figure 4. Output Clocks


Each option has the following two columns:

  • Requested settings
  • Actual settings

The requested settings are the settings that you want to implement, and the actual settings are the settings closest values that can be implemented in the PLL circuit to best approximate the requested settings. Use the values in the actual settings column as a guide to adjust the requested settings. If the requested settings for one of the output clocks cannot be approximated, the ALTPLL parameter editor produces a warning message at the top of every page. To determine the output clocks that contain unachievable settings, turn on Per Clock Feasibility Indicators at the bottom of the ALTPLL parameter editor. The output clock name in red is the name of the clock with unachievable settings. The clock listed in green has no settings issues, and the grayed-out names are the unselected output clocks. You must adjust the requested settings for the affected output clocks to resolve the warning messages, or use another Altera device that meets your desired timing specifications.

To generate an output clock port in your ALTPLL IP core variation, select Use this clock.The output clock port that is to be compensated for is enabled by default. It cannot be disabled, unless you select a different output clock port to be compensated for.

The rest of the options on the page allow you to set the following output clock values:

  • frequency
  • phase shift
  • duty cycle

The phase shift option allows you to set the programmable phase shift for an output clock signals. The smallest phase shift is 1/8th of VCO period. For degree increments, the maximum step size is 45 degrees. You can set smaller steps using the clock multiplication and division factors options. For example, if the post-scale counter is 32, the smallest phase shift step is 0.1°. The up and down buttons let you cycle through phase shift values. Alternatively, you can enter a number in the phase shift field manually instead of using the buttons.

Instead of specifying frequency of the output clock signal, you can also specify the multiplication and division factors of the signal in the requested settings column.

The following figure shows the formula for an output clock frequency.

Figure 5. PLL Output Clock Frequency


The ALTPLL parameter editor calculates the simplest fraction, and displays it in the actual settings column. For example, if the input clock frequency is 100 MHz, and the requested multiplication and division factors are 205 and 1025 respectively, the output clock frequency is calculated as 100 × 205/1025=20 MHz. The actual settings reflect the simplest fraction — the actual multiplication factor is 1, and the actual division factor is 5. You can use the copy button to copy values from the actual settings to the requested settings.

The actual values of multiplication and division factors are affected when you select Use these clock settings for the DPA clock or Set up PLL in LVDS mode.

Select Use these clock settings for the DPA clock if you want the output clock signal of the PLL to drive the input clock port of the DPA block in the ALTLVDS IP core. This option is available only for Stratix III and Stratix IV devices.

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