ALTPLL (Phase-Locked Loop) IP Core User Guide

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ID 683732
Date 6/16/2017
Public
Document Table of Contents
Document Table of Contents x
ALTPLL (Phase-Locked Loop) IP Core User Guide
ALTPLL (Phase-Locked Loop) IP Core User Guide x
ALTPLL Features Ports and Parameters Design Examples Document Revision History
ALTPLL Features x
Phase-Locked Loop Types of PLLs Operation Modes Output Clocks Advanced Features PLL Output Counter Cascading
Phase-Locked Loop x
Building Blocks of a PLL PLL Behavior
Types of PLLs x
Parameter Setting Total Number of PLL Available in Each Supported Device Family
Operation Modes x
Operation Modes Supported in Each Device Family Parameter Settings Determining the PLL Lock Range Expanding the PLL Lock Range Setting Up Stratix III and Stratix IV PLLs for LVDS Interfacing Simulating External Feedback Board Delay
Output Clocks x
Parameter Settings Parameter Settings When “Set up PLL in LVDS mode” Option is Enabled Summary of PLL Output Clocks
Advanced Features x
Advanced Control Signals (pllena, areset, pfdena) Clock Switchover Spread-Spectrum Clocking Gated Lock and Self-Reset Programmable Bandwidth Advanced PLL Parameters PLL Dynamic Reconfiguration Dynamic Phase Configuration
Advanced Control Signals (pllena, areset, pfdena) x
pllena areset pfdena Parameter Settings Summary of Advanced Control Signals
Clock Switchover x
Parameter Settings Summary of Automatic Clock Switchover Feature
Spread-Spectrum Clocking x
Parameter Settings Summary of Spread-Spectrum Clocking Feature
Gated Lock and Self-Reset x
Gated Lock Self-Reset on Loss of Lock Parameter Settings Calculating the Value of Gated Lock Counter Summary of Gated Lock Signals and Self-Reset on Loss of Lock
Programmable Bandwidth x
Parameter Settings Summary of Programmable Bandwidth Support
Advanced PLL Parameters x
Advanced Parameter Settings
PLL Dynamic Reconfiguration x
Parameter Settings Summary of Supported Device Families for PLL Dynamic Reconfiguration Feature
Dynamic Phase Configuration x
Supported Devices Parameter Settings Modifying the PLL Phase Shift Step Resolution Using Advanced Parameters
Ports and Parameters x
ALTPLL Input Ports ALTPLL Output Ports ALTPLL Bidirectional Port ALTPLL Parameters
Design Examples x
Design Files Design Example 1: Differential Clock Design Example 2: Generating Clock Signals
Design Example 1: Differential Clock x
Generating a 166-MHz Differential SSTL External Clock Implementing the ddr_clk Design Functional Results — Simulate the ddr_clk Design in the ModelSim®-Altera Software
Design Example 2: Generating Clock Signals x
Generating 133-MHz, 200-MHz, and 200-MHz Time-Shifted Clocks Implementing the shift_clk Design Simulating the shift_clk Design in the ModelSim-Altera Software
ALTPLL (Phase-Locked Loop) IP Core User Guide

Parameter Settings

Describes how to set the operation mode for the PLL using the ALTPLL parameter editor. The parameter settings are located on the General/Modes page of the ALTPLL parameter editor.

The following figure shows the options you can select from the page.

Figure 2. Operation Mode Options


The following table lists the options you can select from the page.

Table 3.  Operation Mode Options and Descriptions

Option

Description

Use the feedback path inside the PLL

Specify which operation mode to use.

For source-synchronous mode, zero-delay buffer mode, and external feedback mode, you must make PLL Compensation assignments using the Assignment Editor in addition to setting the appropriate mode in the IP core. The assignment allows you to specify an output pin as a compensation target for a PLL in zero-delay buffer mode or external feedback mode, or to specify an input pin or group of input pins as compensation targets for a PLL in source-synchronous mode.

Create an 'fbin' input for an external feedback (External Feedback Mode)

Select this option to set the PLL in external feedback mode. The fbin port is the input port to the PLL from the external feedback path. In this mode, the PLL compensates for the fbin port. The delay between the input clock pin and the feedback clock pin is minimized.

Which output clock will be compensated for?

Specify which output port of the PLL is to be compensated for. The drop down list contains all output clock ports for the selected device. The correct output clock selection depends on the operation mode that you select. For example, for normal mode, select the core output clock. For zero-delay buffer mode or external feedback mode, select the external output clock.

The following figure shows the options you can select from the page.

Figure 3. General Options


The following table lists the options you can select from the page.

Table 4.  Operation Mode Options and Descriptions

Option

Description

Which device speed grade will you be using?

Specify the speed grade if you are not already using a device with the fastest speed. The lower the number, the faster the speed grade.

What is the frequency of the inclock0 input?

Specify the frequency of the input clock signal.

Set up PLL in LVDS mode

Select this option when you want the PLL to supply the necessary clocking signals to the LVDS transmitter or receiver. In this mode, the PLL type and operation mode are forced to fast PLL and normal mode, respectively. This option creates two new output ports —sclkout and enable.

This option is available only for the Arria GX, Stratix II, Stratix II GX, andHardCopy II device families.

Data rate

Specify the data rate for the PLL in LVDS mode. This option is available only if Set up PLL in LVDS mode is enabled.

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