ALTPLL (Phase-Locked Loop) IP Core User Guide

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ID 683732
Date 6/16/2017
Public
Document Table of Contents
Document Table of Contents x
ALTPLL (Phase-Locked Loop) IP Core User Guide
ALTPLL (Phase-Locked Loop) IP Core User Guide x
ALTPLL Features Ports and Parameters Design Examples Document Revision History
ALTPLL Features x
Phase-Locked Loop Types of PLLs Operation Modes Output Clocks Advanced Features PLL Output Counter Cascading
Phase-Locked Loop x
Building Blocks of a PLL PLL Behavior
Types of PLLs x
Parameter Setting Total Number of PLL Available in Each Supported Device Family
Operation Modes x
Operation Modes Supported in Each Device Family Parameter Settings Determining the PLL Lock Range Expanding the PLL Lock Range Setting Up Stratix III and Stratix IV PLLs for LVDS Interfacing Simulating External Feedback Board Delay
Output Clocks x
Parameter Settings Parameter Settings When “Set up PLL in LVDS mode” Option is Enabled Summary of PLL Output Clocks
Advanced Features x
Advanced Control Signals (pllena, areset, pfdena) Clock Switchover Spread-Spectrum Clocking Gated Lock and Self-Reset Programmable Bandwidth Advanced PLL Parameters PLL Dynamic Reconfiguration Dynamic Phase Configuration
Advanced Control Signals (pllena, areset, pfdena) x
pllena areset pfdena Parameter Settings Summary of Advanced Control Signals
Clock Switchover x
Parameter Settings Summary of Automatic Clock Switchover Feature
Spread-Spectrum Clocking x
Parameter Settings Summary of Spread-Spectrum Clocking Feature
Gated Lock and Self-Reset x
Gated Lock Self-Reset on Loss of Lock Parameter Settings Calculating the Value of Gated Lock Counter Summary of Gated Lock Signals and Self-Reset on Loss of Lock
Programmable Bandwidth x
Parameter Settings Summary of Programmable Bandwidth Support
Advanced PLL Parameters x
Advanced Parameter Settings
PLL Dynamic Reconfiguration x
Parameter Settings Summary of Supported Device Families for PLL Dynamic Reconfiguration Feature
Dynamic Phase Configuration x
Supported Devices Parameter Settings Modifying the PLL Phase Shift Step Resolution Using Advanced Parameters
Ports and Parameters x
ALTPLL Input Ports ALTPLL Output Ports ALTPLL Bidirectional Port ALTPLL Parameters
Design Examples x
Design Files Design Example 1: Differential Clock Design Example 2: Generating Clock Signals
Design Example 1: Differential Clock x
Generating a 166-MHz Differential SSTL External Clock Implementing the ddr_clk Design Functional Results — Simulate the ddr_clk Design in the ModelSim®-Altera Software
Design Example 2: Generating Clock Signals x
Generating 133-MHz, 200-MHz, and 200-MHz Time-Shifted Clocks Implementing the shift_clk Design Simulating the shift_clk Design in the ModelSim-Altera Software
ALTPLL (Phase-Locked Loop) IP Core User Guide

Modifying the PLL Phase Shift Step Resolution Using Advanced Parameters

The finest phase shift step resolution you can get in the ALTPLL IP core is 1/8th of the VCO period. If the VCO frequency is at the lower end of the supported VCO range, the phase shift step resolution may be larger than you would prefer for your design.

You can modify your phase shift resolution using the dynamic phase reconfiguration feature of the PLL. If you want to modify the phase shift resolution without the dynamic phase reconfiguration feature enabled, perform the following steps:

  1. Create an ALTPLL instance. Make sure you specify the speed grade of your target device and the PLL type.
  2. On the PLL Reconfiguration page, turn on Create Optional Inputs for Dynamic Phase Reconfiguration and Enable Phase Shift Step Resolution Edit.
  3. On the Output Clocks page, set your desired phase shift for each required output clock. Click More Details to see the internal PLL settings. Note all of the settings shown.
  4. On the Bandwidth/SS page, click More Details to see the internal PLL settings. Note all of the settings shown.
  5. On the Inputs/Lock page, turn on Create output file(s) using the ‘Advanced’ PLL Parameters.
  6. Return to the PLL Reconfiguration page and turn off Create Optional Inputs for Dynamic Phase Reconfiguration.
  7. Click Finish to generate the PLL instantiation file(s).
    When using Advanced Parameters, the PLL wrapper file (<ALTPLL_instantiation_name>.v|.vhd) is written in a format that allows you to identify the PLL parameters. The parameters are listed in the Generic Map section of the VHDL file, or in the defparam section of the Verilog file.
  8. Open your PLL instantiation wrapper file and locate either the Generic Map or the defparam section.
  9. Modify the settings to match the settings that you noted in steps 3 and 4.
  10. Save the PLL instantiation wrapper file and compile your design.
  11. Verify that the output clock frequencies and phases are correct in the PLL Usage report located under Resource Section of the Fitter folder in the Compilation Report.
By using this technique, you can apply valid PLL parameters as provided by the ALTPLL parameter editor to optimize the settings for your design.

Alternatively, you can leave the dynamic phase reconfiguration option enabled and tie the relevant input ports—phasecounterselect[3..0], phaseupdown, phasestep, and scanclk—to constants, if you prefer not to manually edit the PLL wrapper file using Advanced PLL Parameters option.

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