ALTPLL (Phase-Locked Loop) IP Core User Guide

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ID 683732
Date 6/16/2017
Public
Document Table of Contents
Document Table of Contents x
ALTPLL (Phase-Locked Loop) IP Core User Guide
ALTPLL (Phase-Locked Loop) IP Core User Guide x
ALTPLL Features Ports and Parameters Design Examples Document Revision History
ALTPLL Features x
Phase-Locked Loop Types of PLLs Operation Modes Output Clocks Advanced Features PLL Output Counter Cascading
Phase-Locked Loop x
Building Blocks of a PLL PLL Behavior
Types of PLLs x
Parameter Setting Total Number of PLL Available in Each Supported Device Family
Operation Modes x
Operation Modes Supported in Each Device Family Parameter Settings Determining the PLL Lock Range Expanding the PLL Lock Range Setting Up Stratix III and Stratix IV PLLs for LVDS Interfacing Simulating External Feedback Board Delay
Output Clocks x
Parameter Settings Parameter Settings When “Set up PLL in LVDS mode” Option is Enabled Summary of PLL Output Clocks
Advanced Features x
Advanced Control Signals (pllena, areset, pfdena) Clock Switchover Spread-Spectrum Clocking Gated Lock and Self-Reset Programmable Bandwidth Advanced PLL Parameters PLL Dynamic Reconfiguration Dynamic Phase Configuration
Advanced Control Signals (pllena, areset, pfdena) x
pllena areset pfdena Parameter Settings Summary of Advanced Control Signals
Clock Switchover x
Parameter Settings Summary of Automatic Clock Switchover Feature
Spread-Spectrum Clocking x
Parameter Settings Summary of Spread-Spectrum Clocking Feature
Gated Lock and Self-Reset x
Gated Lock Self-Reset on Loss of Lock Parameter Settings Calculating the Value of Gated Lock Counter Summary of Gated Lock Signals and Self-Reset on Loss of Lock
Programmable Bandwidth x
Parameter Settings Summary of Programmable Bandwidth Support
Advanced PLL Parameters x
Advanced Parameter Settings
PLL Dynamic Reconfiguration x
Parameter Settings Summary of Supported Device Families for PLL Dynamic Reconfiguration Feature
Dynamic Phase Configuration x
Supported Devices Parameter Settings Modifying the PLL Phase Shift Step Resolution Using Advanced Parameters
Ports and Parameters x
ALTPLL Input Ports ALTPLL Output Ports ALTPLL Bidirectional Port ALTPLL Parameters
Design Examples x
Design Files Design Example 1: Differential Clock Design Example 2: Generating Clock Signals
Design Example 1: Differential Clock x
Generating a 166-MHz Differential SSTL External Clock Implementing the ddr_clk Design Functional Results — Simulate the ddr_clk Design in the ModelSim®-Altera Software
Design Example 2: Generating Clock Signals x
Generating 133-MHz, 200-MHz, and 200-MHz Time-Shifted Clocks Implementing the shift_clk Design Simulating the shift_clk Design in the ModelSim-Altera Software
ALTPLL (Phase-Locked Loop) IP Core User Guide

Generating a 166-MHz Differential SSTL External Clock

To generate a 166-MHz Differential SSTL external clock, follow these steps:

Download and unzip the ddr_clk.zip .

  1. In the Quartus® Prime software, open the project file \ddr_clk\ddr_clk.qpf.
  2. Open the top-level \ddr_clk\ddr_clk.bdf file. You will complete this project in this example.
  3. Click Tools > IP Catalog. Then expand the I/O folder and select ALTPLL
  4. In Which type of output file do you want to create?, select AHDL.
  5. For What name do you want for the output file?, name the output file ddr_pll.
  6. For What is the frequency of the inclock0 input?, type 33.33, and select MHz.
  7. Under PLL type, click Select the PLL type automatically.
  8. Under Operation mode, select Create an 'fbin' input for an external feedback (External Feedback Mode).
  9. Under Operation mode, for Which output clock will have a board level connection?, select e0 from the drop‑down menu.
  10. In the Dynamic configuration section, turn off Create optional inputs for dynamic reconfiguration.
  11. In the Optional inputs sections:
    1. Turn on Create an ‘pllena’ input to selectively enable the PLL.
    2. Turn on Create an ‘areset’ input to asynchronously reset the PLL.
    3. Turn off Create an ‘pfdena’ input to selectively enable the phase/frequency detector.
  12. In the Lock output section, turn on Create ‘locked’ output.
  13. Leave the remaining options at their default settings.
  14. Click the Output Clocks tab.
  15. Click extclk e0.
  16. Turn on Use this clock.
  17. Turn on Enter output clock parameters, and in the Clock multiplication factor box, type 5.
  18. In the Clock division factor box, type 1.
  19. In the Clock duty cycle (%) box, type 50.00.
  20. Click Next.
  21. On page 14, repeat step 16 through step 19 for extclk e1.
  22. Click Next.
  23. On page 15, repeat step 16 through step 19 for extclk e2.
  24. Click Next.
  25. On page 16, repeat step 16 through step 19 for extclk e3.
  26. Click Next. Page 17 appears. No input is required for this page.
  27. Click Next. Page 18 appears.
  28. On page 18, ensure that the Text Design File (.tdf), Pin Planner File (.ppf), AHDL Include File (.inc), Block Symbol File (.bsf), and Sample waveforms in summary file (.html and .jpg) are turned on.
  29. Click Finish. The ddr_pll module is built.
  30. In the Symbol dialog box of the .bdf file, click OK.
  31. Move the pointer to place the ddr_pll symbol between the input and output ports in the ddr_clk.bdf file, connecting the inputs and outputs to the symbol. Click to place the symbol.
  32. Save the design.
The following figure shows a completed design file.
Figure 21. ALTPLL ddr_pll Design Schematic


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