PHY Lite for Parallel Interfaces Intel® FPGA IP User Guide

ID 683716
Date 7/15/2024
Public
Document Table of Contents

6.5.2. Reference Clock

Intel recommends that you source the reference clock to the PHY Lite for Parallel Interfaces Intel® FPGA IP from a dedicated clock pin. Use the clock pin in one of the I/O banks used by the PHY Lite for Parallel Interfaces Intel® FPGA IP. You must use contiguous I/O banks to implement multiple interfaces (consisting of a combination of External Memory Interface and PHY Lite for Parallel Interfaces Intel® FPGA IP). If you use the same reference clock for these interfaces, place the reference clock in any of the contiguous I/O banks.

Note: For Quartus® Prime software version 18.1 or later, you may see error warning message for design with encrypted IOPLL IP. The auto-generated .sdc files of the IOPLL IP are not supported if you use encryption. You must manually create the .sdc file using create_clock and create_generated_clock to replace the auto-generated .sdc file in the design for refclk and output clocks.