Visible to Intel only — GUID: bhc1410941960764
Ixiasoft
Visible to Intel only — GUID: bhc1410941960764
Ixiasoft
7.5.2. Reference Clock
The reference clock of the PHY Lite for Parallel Interfaces FPGA IP must be sourced from an external clock source to a dedicated clock pin. Use the clock pin in one of the I/O banks used by the PHY Lite for Parallel Interfaces FPGA IP. You must use contiguous I/O banks to implement multiple interfaces (consisting of a combination of External Memory Interface and PHY Lite for Parallel Interfaces FPGA IP). If you use the same reference clock for these interfaces, place the reference clock in any of the contiguous I/O banks.
The use of an IOPLL clock output to source the reference clock of the PHY Lite for Parallel Interfaces FPGA IP is not supported.