Visible to Intel only — GUID: bhc1410941960764
Ixiasoft
Visible to Intel only — GUID: bhc1410941960764
Ixiasoft
6.5.2. Reference Clock
Intel recommends that you source the reference clock to the PHY Lite for Parallel Interfaces Intel® FPGA IP from a dedicated clock pin. Use the clock pin in one of the I/O banks used by the PHY Lite for Parallel Interfaces Intel® FPGA IP. You must use contiguous I/O banks to implement multiple interfaces (consisting of a combination of External Memory Interface and PHY Lite for Parallel Interfaces Intel® FPGA IP). If you use the same reference clock for these interfaces, place the reference clock in any of the contiguous I/O banks.