PHY Lite for Parallel Interfaces Intel® FPGA IP User Guide

ID 683716
Date 7/15/2024
Public
Document Table of Contents

2.5.1.2.2. Generate the Simulation Design Example with Dynamic Reconfiguration

The make_sim_design.tcl generates a simulation design example and tool specific scripts to compile and elaborate the necessary files.

To generate the design example for a Verilog or a mixed-language simulator, run the following script at the end of IP generation:

quartus_sh -t make_sim_design.tcl VERILOG

To generate the design example for a VHDL-only simulator, run the following script:

quartus_sh -t make_sim_design.tcl VHDL

This script generates a sim directory containing one subdirectory for each supported simulation tool. Each subdirectory contains the specific scripts to run simulation using the corresponding tool.

Figure 32. High-Level View of the Simulation Design Example with Dynamic ReconfigurationThis figure shows a high-level view of the simulation design example with dynamic reconfiguration, consisting of a PHY Lite IP instance, Calibration IP, IOSSM Tester, IO Model, and PHYLite Interface modules.