Intel® Acceleration Stack for Intel® Xeon® CPU with FPGAs 1.0 Errata

ID 683637
Date 6/22/2018
Public

Intel® Acceleration Stack for Intel® Xeon® CPU with FPGAs 1.0 Errata

Updated for:
Intel® Acceleration Stack for Intel® Xeon® CPU with FPGAs 1.0 Production
This document provides information about errata affecting the Intel® Acceleration Stack for Intel® Xeon® CPU with FPGAs.
Issue Affected Versions Planned Fix
Flash Fallback Does Not Meet PCIe Timeout Acceleration Stack 1.0 Production No Planned Fix
Unsupported Transaction Layer Packet Types Acceleration Stack 1.0 Production No Planned Fix
JTAG Timing Failures May Be Reported in the FPGA Interface Manager Acceleration Stack 1.0 Production Acceleration Stack 1.1
fpgabist Tool Does Not Pass Hexadecimal Bus Numbers Properly Acceleration Stack 1.0 Production Acceleration Stack 1.1
Possible Low dma_afu Bandwidth Due to memcpy Function Acceleration Stack 1.0 Beta and Production Acceleration Stack 1.1
regress.sh -r Option Does Not Work With dma_afu Acceleration Stack 1.0 Production No planned fix

The table below can be used as a reference to identify the FPGA Interface Manager (FIM), Open Programmable Acceleration Engine (OPAE) and Intel® Quartus® Prime Pro Edition version that corresponds to your software stack release.

Table 1.   Intel® Acceleration Stack 1.0 Reference Table
Intel® Acceleration Stack Version Boards FIM Version (PR Interface ID) OPAE Version Intel® Quartus® Prime Pro Edition
1.0 Production1 Intel® PAC with Intel® Arria® 10 GX FPGA ce489693-98f0-5f33-946d-560708be108a 0.13.1 17.0.0
1 The factory partition of the configuration flash contains the Acceleration Stack 1.0 Alpha version. When the image in the user partition cannot be loaded, a flash failover occurs and the factory image is loaded instead. After a flash failover occurs, the PR ID reads as d4a76277-07da-528d-b623-8b9301feaffe.