Intel® Stratix® 10 Avalon® -MM Hard IP for PCIe* Design Example User Guide

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ID 683616
Date 11/06/2017
Public

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Document Table of Contents
Document Table of Contents x
1. Quick Start Guide 2. Design Example Description A. Document Revision History for the Intel® Stratix® 10 Avalon® -MM Hard IP for PCIe* Design Example User Guide
1. Quick Start Guide x
1.1. Design Components 1.2. Directory Structure 1.3. Generating the Design Example 1.4. Simulating the Design Example 1.5. Compiling the Design Example and Programming the Device 1.6. Installing the Linux Kernel Driver 1.7. Running the Design Example Application
2. Design Example Description x
2.1. Functional Description for the Simple DMA Design Example
2.1. Functional Description for the Simple DMA Design Example x
2.1.1. Serial Data Signals
A. Document Revision History for the Intel® Stratix® 10 Avalon® -MM Hard IP for PCIe* Design Example User Guide x
A.1. Intel® Stratix® 10 Avalon® -MM Hard IP for PCIe* Design Example User Guide Revision History
1. Quick Start Guide
2. Design Example Description
A. Document Revision History for the Intel® Stratix® 10 Avalon® -MM Hard IP for PCIe* Design Example User Guide

A.1. Intel® Stratix® 10 Avalon® -MM Hard IP for PCIe* Design Example User Guide Revision History

Date Software Version Changes
November 2017 17.1 Made the following changes:
  • Added compilation support.
  • Changed design example to demonstrate the simple DMA design.
  • Added Linux driver for hardware example.
  • Added simulation support for NCSim.
  • Revised Generating the Design topic to create a single .ip for PCIe* instead of a complete system design. Generating the testbench creates a design example from the .ip .
  • Added web link to information on using the PCIe* Link Inspector.
May 2017 Quartus®Prime Pro v17.1 Stratix 10 ES Editions Initial release.
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