Intel® MAX® 10 Analog to Digital Converter User Guide

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ID 683596
Date 1/03/2024
Public
Document Table of Contents
Document Table of Contents x
1. Intel® MAX® 10 Analog to Digital Converter Overview 2. Intel® MAX® 10 ADC Architecture and Features 3. Intel® MAX® 10 ADC Design Considerations 4. Intel® MAX® 10 ADC Implementation Guides 5. Modular ADC Core Intel® FPGA IP and Modular Dual ADC Core Intel® FPGA IP References 6. Intel® MAX® 10 Analog to Digital Converter User Guide Archives 7. Document Revision History for Intel® MAX® 10 Analog to Digital Converter User Guide
1. Intel® MAX® 10 Analog to Digital Converter Overview x
1.1. ADC Block Counts in Intel® MAX® 10 Devices 1.2. ADC Channel Counts in Intel® MAX® 10 Devices 1.3. Intel® MAX® 10 ADC Vertical Migration Support 1.4. Intel® MAX® 10 Single or Dual Supply Devices 1.5. Intel® MAX® 10 ADC Conversion
1.5. Intel® MAX® 10 ADC Conversion x
1.5.1. Voltage Representation Conversion
2. Intel® MAX® 10 ADC Architecture and Features x
2.1. Intel® MAX® 10 ADC Hard IP Block 2.2. Modular ADC Core and Modular Dual ADC Core IP Cores 2.3. Intel FPGA ADC HAL Driver 2.4. ADC Toolkit for Testing ADC Performance 2.5. ADC Logic Simulation Output
2.1. Intel® MAX® 10 ADC Hard IP Block x
2.1.1. ADC Block Locations 2.1.2. Single or Dual ADC Devices 2.1.3. ADC Analog Input Pins 2.1.4. ADC Prescaler 2.1.5. ADC Clock Sources 2.1.6. ADC Voltage Reference 2.1.7. ADC Temperature Sensing Diode 2.1.8. ADC Sequencer 2.1.9. ADC Timing
2.1.7. ADC Temperature Sensing Diode x
2.1.7.1. Temperature Measurement Code Conversion 2.1.7.2. Temperature Measurement Sampling Rate
2.1.8. ADC Sequencer x
2.1.8.1. Guidelines: ADC Sequencer in Modular Dual ADC Core IP Core
2.2. Modular ADC Core and Modular Dual ADC Core IP Cores x
2.2.1. Modular ADC Core IP Core Configuration Variants 2.2.2. Modular ADC Core and Modular Dual ADC Core IP Cores Architecture
2.2.1. Modular ADC Core IP Core Configuration Variants x
2.2.1.1. Configuration 1: Standard Sequencer with Avalon-MM Sample Storage 2.2.1.2. Configuration 2: Standard Sequencer with Avalon-MM Sample Storage and Threshold Violation Detection 2.2.1.3. Configuration 3: Standard Sequencer with External Sample Storage 2.2.1.4. Configuration 4: ADC Control Core Only
2.2.2. Modular ADC Core and Modular Dual ADC Core IP Cores Architecture x
2.2.2.1. ADC Control Core 2.2.2.2. Sequencer Core 2.2.2.3. Sample Storage Core 2.2.2.4. Response Merge Core 2.2.2.5. Dual ADC Synchronizer Core 2.2.2.6. Threshold Detection Core
2.5. ADC Logic Simulation Output x
2.5.1. Fixed ADC Logic Simulation Output 2.5.2. User-Specified ADC Logic Simulation Output
3. Intel® MAX® 10 ADC Design Considerations x
3.1. Guidelines: ADC Ground Plane Connection 3.2. Guidelines: Board Design for Power Supply Pin and ADC Ground (REFGND) 3.3. Guidelines: Board Design for Analog Input 3.4. Guidelines: Board Design for ADC Reference Voltage Pin
4. Intel® MAX® 10 ADC Implementation Guides x
4.1. Creating Intel® MAX® 10 ADC Design 4.2. Customizing and Generating Modular ADC Core IP Core 4.3. Parameters Settings for Generating ALTPLL IP Core 4.4. Parameters Settings for Generating Modular ADC Core or Modular Dual ADC Core IP Core 4.5. Completing ADC Design
5. Modular ADC Core Intel® FPGA IP and Modular Dual ADC Core Intel® FPGA IP References x
5.1. Modular ADC Core Parameters Settings 5.2. Modular Dual ADC Core Parameters Settings 5.3. Valid ADC Sample Rate and Input Clock Combination 5.4. Modular ADC Core and Modular Dual ADC Core Interface Signals 5.5. Modular ADC Core Register Definitions 5.6. ADC HAL Device Driver for Nios® Processor
5.1. Modular ADC Core Parameters Settings x
5.1.1. Modular ADC Core IP Core Channel Name to Intel® MAX® 10 Device Pin Name Mapping
5.2. Modular Dual ADC Core Parameters Settings x
5.2.1. Modular Dual ADC Core IP Core Channel Name to Intel® MAX® 10 Device Pin Name Mapping
5.4. Modular ADC Core and Modular Dual ADC Core Interface Signals x
5.4.1. Command Interface of Modular ADC Core and Modular Dual ADC Core 5.4.2. Response Interface of Modular ADC Core and Modular Dual ADC Core 5.4.3. Threshold Interface of Modular ADC Core and Modular Dual ADC Core 5.4.4. CSR Interface of Modular ADC Core and Modular Dual ADC Core 5.4.5. IRQ Interface of Modular ADC Core and Modular Dual ADC Core 5.4.6. Peripheral Clock Interface of Modular ADC Core and Modular Dual ADC Core 5.4.7. Peripheral Reset Interface of Modular ADC Core and Modular Dual ADC Core 5.4.8. ADC PLL Clock Interface of Modular ADC Core and Modular Dual ADC Core 5.4.9. ADC PLL Locked Interface of Modular ADC Core and Modular Dual ADC Core
5.5. Modular ADC Core Register Definitions x
5.5.1. Sequencer Core Registers 5.5.2. Sample Storage Core Registers
5.6. ADC HAL Device Driver for Nios® Processor x
5.6.1. Driver API
1. Intel® MAX® 10 Analog to Digital Converter Overview
2. Intel® MAX® 10 ADC Architecture and Features
3. Intel® MAX® 10 ADC Design Considerations
4. Intel® MAX® 10 ADC Implementation Guides
5. Modular ADC Core Intel® FPGA IP and Modular Dual ADC Core Intel® FPGA IP References
6. Intel® MAX® 10 Analog to Digital Converter User Guide Archives
7. Document Revision History for Intel® MAX® 10 Analog to Digital Converter User Guide

2.2. Modular ADC Core and Modular Dual ADC Core IP Cores

You can use the Modular ADC Core and Modular Dual ADC Core IP cores to generate soft IP controllers for the ADC hard IP blocks in Intel® MAX® 10 devices.

There are two ADC IP cores:

  • Modular ADC Core IP core—each instance can control one ADC hard IP block. In a dual ADC device, you can instantiate one Modular ADC Core IP core instance for each ADC block. However, both instances are asynchronous to each other.
  • Modular Dual ADC Core IP core—you can control both ADC hard IP block with a single IP instance.
    • For the analog input pins (ANAIN1 and ANAIN2) in both ADC hard IP blocks, the measurement is synchronous.
    • For the dual function input pins, there are some measurement timing differences caused by the routing latency.

You can perform the following functions with the Modular ADC Core or Modular Dual ADC Core IP core parameter editor:

  • Configure the ADC clock, sampling rate, and reference voltage.
  • Select which analog input channels that the ADC block samples.
  • Configure the threshold value to trigger a threshold violation notification.
  • Set up a conversion sequence to determine which channel requires more frequent attention.

Section Content
Modular ADC Core IP Core Configuration Variants
Modular ADC Core and Modular Dual ADC Core IP Cores Architecture

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